56-Pin Quad Flatpack No-Lead Logic Package

1 Application ReportSCEA032 - March 2003156-Pin quad Flatpack No-Lead Logic PackageFrank Mortan and Lance WrightSLL Package DevelopmentABSTRACTT exas Instruments (TI) quad Flatpack No-Lead (QFN) 56-terminal Package complies withJEDEC standard MO-220, allows for board miniaturization, and holds several advantagesover traditional SOIC, TQFP, TSSOP, and TVSOP packaging. This Package , designatedRGQ by TI, physically is smaller than traditional leaded solutions, has a smaller routing area,improved thermal performance, and improved electrical parasitics. Additionally, the absenceof external leads eliminates bent-lead concerns and issues.

2 This QFN Package is packed toindustry-standard tape-and-reel specifications. Package marking is in accordance with .. 2 Industry Requirements3.. 3 Physical Description3.. Package Characteristics3.. Package Nomenclature5.. Electrical Performance5.. Power Dissipation6.. Board-Level Reliability9.. Package Reliability10.. 4 Board-Level Assembly11.. PCB Design Guidelines11.. Stencil Design12.. Component Placement and Reflow13.. Rework ..15.. 5 Tape and Reel16.. Material Specifications16.. Shipping Labels18.. Dry-Pack Requirements for Moisture-Sensitive Material18.. 6 Symbolization18.

3 7 Test Sockets19.. 8 Features and Benefits19.. 9 Conclusion20.. 10 Acknowledgments20.. Trademarks are the property of their respective quad Flatpack No-Lead Logic Package11 References20.. List of Figures1. 56 RGQ Package Drawing4.. 2. Improvement in Inductance and Capacitance of RGQ vs Alternative packages (Modeled Data)5.. 3. 56 RGQ JA vs Traditional Package Alternatives7.. 4. The Effect of Thermal Vias7.. 5. Derating of 56 RGQ per JESD 51-3 (Low Effective Thermal Conductivity) Board8.. 6. Derating of 56 RGQ per JESD 51-5 (High Effective Thermal Conductivity) Board8.. 7. Derating of 56 RGQ per JESD 51-7 (High Effective Thermal Conductivity) Board9.

4 8. Recommended Land-Pad Design for the 56 RGQ11.. 9. Recommended Stencil Design for the 56 RGQ13.. 10. Generic SnPb-Paste Reflow Profile (Image Courtesy of Senju Metal Industry Co., Ltd.)14.. 11. Carrier Tape Drawing17.. 12. Reel Drawing and Specifications17.. 13. Pin-1 Orientation of QFN Packages18.. List of Tables1. 56 RGQ Physical Attributes3.. 2. 56 RGQ Compared to Alternative Package Solutions5.. 3. 56 RGQ Thermal Summary6.. 4. Package -Reliability Test Matrix10.. 5. Carrier-Tape Dimensions in Millimeters16.. 6. Device-Marking Guidelines19.. 1 IntroductionThe Texas Instruments (TI) 56-Pin QFN Package , designated RGQ, is a JEDEC standardMO-220-compliant leadless Package that has several advantages over traditional SOIC, TQFP,TSSOP, and TVSOP packaging.

5 The RGQ Package physically is smaller than traditional leadedsolutions, has a smaller routing area, improved thermal performance, and improved electricalparasitics over leaded alternatives. Additionally, the absence of external leads eliminatesbent-lead concerns and issues. The RGQ Package was developed for the 13-bit to 26-bitregistered-buffer function, SN74 SSTV16859, to meet the requirements and board-sizerestrictions of the memory industry s newest low-profile DDR registered dual-inline memorymodule (RDIMM). The RGQ Package is a two-device alternative to the single-device BGAsolution for DDR RDIMM applications in situations where simpler printed circuit board (PCB)fabrication is required, due either to capability or to assembly constraints.

6 At this time, theSN74 SSTV16859 is the only device offered in the RGQ Package . More devices will be releasedas market interest 56-Pin quad Flatpack No-Lead Logic Package2 Industry RequirementsThe consumer-electronics industry is focused on product miniaturization as a result of consumerdemands for smaller and better-performing products. DRAM modules have migrated in the samedirection as most electronic products. The latest low-profile, stacked, TSOP-based memorymodules have eliminated the 64-pin TSSOP Package previously used for registered buffers, inlieu of either BGA or QFN, to meet the DIMM height reduction from inches to inches.

7 Toattain smaller products, electronic manufacturers require smaller packages (area and height) toreduce board size and weight. Improved heat dissipation and electrical parasitics also will berequired as the packages and systems shrink in size. Heat dissipation is important becausepackages with better thermal dissipation typically can run at faster speeds, if required, andpackages with better electrical parasitics generally have lower signal noise. Both of these areimportant for high-end processors to deliver a stable, clean signal output. TI has selected theRGY Package as one alternative to address these industry CharacteristicsTable 1 summarizes attributes of the TI 56-Pin QFN Package (RGQ).

8 Figure 1 shows thepackage dimensions, and Table 2 provides a comparison of RGQ physical attributes toalternative Package 1. RGQ Physical AttributesAttribute56 RGQPin count56 Square/RectangularSquarePackage length (mm) width (mm) finger length (mm) finger width (mm) pad length (mm) pad width (mm) thickness (mm) weight (g) sensitivityLevel 3, 235 CLead finishSnPbShipping media, tape and reel (units/reel)2000 SCEA032456-Pin quad Flatpack No-Lead Logic Package56X 0,237,858,15D43425610,08 C17,657,85560,50A+0,07 0,050,050,10 MCMCB292814150,30 Seating Plane0,000,05C7,858,15AB5,355,054,354,65 4342292815140,80 Min0,90 MaxPin 1 IdentifierExposed Thermal Die PadPin 1 Identifier4X0,506,5056 XSq0,20 Nominal Lead FrameTop ViewSide ViewBottom ViewDimensions are in 1.

9 56 RGQ Package DrawingSCEA0325 56-Pin quad Flatpack No-Lead Logic PackageTable 2. 56 RGQ Compared to Alternative Package SolutionsAttribute64-TSSOP(DGG)56-TSSOP( DGG)56-TVSOP(DGV)64-TQFP (PAG)56-QFN (56 RGQ)Length (mm) (mm) (mm), (mm) (mm2) (g) Area NomenclatureGenerically, this Package is referred to in this application report as QFN. The TI packagedesignator for this 56-Pin QFN Package is RGQ. The designator is extended to RGQR todesignate packing for shipment in tape and reel, as explained in section PerformanceThe unique construction of QFN packages reduces both inductance and capacitance.

10 Theexposed thermal die pad of the QFN Package is at board level, following assembly, whichminimizes inductance when grounded. Figure 2 compares the percentage improvement of theRGQ Package to other packaging options. These models take into account the exposed pad andthe fact that the pad is grounded to the board of QFN Package Over AlternativesL (nH)C (pF)Figure 2. Improvement in Inductance and Capacitance of RGQ vs Alternative packages (Modeled Data)SCEA032656-Pin quad Flatpack No-Lead Logic DissipationWhen thermal dissipation is crucial, the QFN Package has an advantage over standarddual- and quad -leaded packages .