AM1802 ARM Microprocessor - TI.com

1 ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityAM1802 SPRS710E NOVEMBER2010 REVISEDMARCH2014AM1802 ARM Microprocessor1 300-MHzARM926EJ-S RISCMPU Two SerialPeripheralInterfaces(SPIs)Eachwith MultipleChipSelects ARM926EJ-SCore One MultimediaCard(MMC)/SecureDigital(SD) 32-Bitand 16-Bit( Thumb ) InstructionsCardInterfaceswith SecureDataI/O (SDIO) Single-CycleMACI nterfaces ARMJ azelle Technology One Masterand SlaveInter-IntegratedCircuit( I2C EmbeddedICE-RT for Real-TimeDebugBus ) ARM9 MemoryArchitecture OTGPort with IntegratedPHY(USB0) 16 KBof InstructionCache High-and Full-SpeedClient 16 KBof DataCache High-,Full-,and Low-SpeedHost 8KB of RAM(VectorTable) End Point0 (Control) 64 KBof ROM End Points1, 2, 3, 4 (Control,Bulk,Interruptor EnhancedDirectMemoryAccessController3 ISOC)RX and TX(EDMA3): One MultichannelAudioSerialPort (McASP): 2 ChannelControllers Transmitand ReceiveClocks 3 TransferControllers Two ClockZonesand 16 SerialDataPins 64 IndependentDMAC hannels SupportsTDM,I2S, and SimilarFormats 16 QuickDMAC hannels DIT-Capable ProgrammableTransferBurstSize FIFOB uffersfor Transmitand Receive 128 KBof On-ChipMemory 10/100 MbpsEthernetMAC(EMAC): (Exceptfor USBand ) MII Media-IndependentInterface Two ExternalMemoryInterfaces: RMIIR educedMedia-IndependentInterface EMIFA ManagementDataI/O (MDIO)Module NOR(8- or 16-Bit-WideData) Real-TimeClock(RTC)with 32-kHzOscillatorand NAND(8- or 16-Bit-WideData)SeparatePowerRail 16-BitSDRAM with 128-MBAddressSpace Three64-BitGeneral-PurposeTimers(Each DDR2/MobileDDRM emoryControllerwith oneConfigurableas Two 32-BitTimers)of the following.

2 One 64-BitGeneral-Purposeor WatchdogTimer 16-BitDDR2 SDRAM with 256-MBAddress(Configurableas Two 32-BitGeneral-PurposeSpaceTimers) 16-BitmDDRSDRAM with 256-MBAddress Packages:Space 361-BallPb-FreePlasticBall Grid Array(PBGA) ThreeConfigurable16550-TypeUARTM odules:[ZCES uffix], Pitch WithModemControlSignals 361-BallPBGA[ZWTS uffix], Pitch 16-ByteFIFO IndustrialTemperature 16x or 13x Medical,Healthcare,and Fitness ePOS BuildingAutomation1An IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand NOVEMBER2010 AM1802 ARMmicroprocessoris a low-powerapplicationsprocessorbasedon deviceenablesoriginal-equipmentmanufactu rers(OEMs)and original-designmanufacturers(ODMs)to quicklybringto marketdevicesfeaturingrobustoperatingsys temssupport,rich userinterfaces,andhighprocessingperforma ncelife throughthe maximumflexibilityof a a 32-bitRISC processorcorethatperforms32-bitor 16-bitinstructionsandprocesses32-bit,16- bit,or coreusespipeliningso that all partsof the processorandmemorysystemcan coprocessor15 (CP15),protectionmodule,anddataandprogra mmemorymanagementunits(MMUs)

3 With ARMcoreprocessorhas separate16-KBinstructionand four-wayassociativewith virtualindexvirtualtag (VIVT).TheARMcorealso has 8KB of RAM(VectorTable)and 64 KBof peripheralset includes:a 10/100 MbpsEthernetmediaaccesscontroller(EMAC)w ith a managementdatainput/output(MDIO)module; ;oneinter-integratedcircuit(I2C Bus)interface;one multichannelaudioserialport (McASP)with16 serializersand FIFO buffers;two serialperipheralinterfaces(SPIs)withmult iplechipselects;four64-bitgeneral-purpos etimerseachconfigurable(oneconfigurablea s watchdog);a configurable16-bithost-portinterface(HPI );up to 9 banksof general-purposeinput/output(GPIO)pins,wi theachbankcontaining16 pinswithprogrammableinterruptand eventgenerationmodes,multiplexedwithothe rperipherals;threeUART interfaces(eachwithRTSand CTS);two externalmemoryinterfaces:an asynchronousand SDRAM externalmemoryinterface(EMIFA)for slowermemoriesor peripherals;and a higherspeedDDR2 EMAC providesan efficientinterfacebetweenthe deviceand a EMAC supportsboth10 Base-Tand 100 Base-TX,or 10 Mbpsand 100 Mbpsin eitherhalf-or ,anMDIO interfaceis availablefor EMAC supportsbothMII and rich peripheralset providesthe abilityto controlexternalperipheraldevicesand detailson eachof the peripherals,see the relatedsectionsin this documentandthe a completeset of developmenttoolsfor the ,and scheduling,and a Windows debuggerinterfacefor visibilityinto (361)16,00mm x 16,00mmAM1802 ZCENFBGA(361)13,00mm x 13,00mm2AM1802 ARMM icroprocessorCopyright 2010 2014,TexasInstrumentsIncorporatedSubmitD ocumentationFeedbackProductFolderLinks.

4 AM1802 Switched Central Resource (SCR)16 KBI-Cache16 KBD-Cache4KB ETBARM926EJ-S CPUWith MMUARM SubsystemJTAG InterfaceSystem ControlInputClock(s)64KB ROM8KB RAM(Vector Table)Power/SleepControllerPinMultiplexi ngPLL/ClockGeneratorw/OSCG eneral-PurposeTimer (x3)Serial InterfacesAudio PortsMcASPw/FIFODMAP eripheralsInternal Memory128 KBRAME xternal Memory InterfacesConnectivityEDMA3(x2)EMIFA(8b/ 16B)NAND/Flash16b SDRAMDDR2/MDDRC ontrollerRTC/32-kHzOSCI C2(x1)SPI(x2)UART(x3)EMAC10/100(MII/RMII ) CtlrPHYMMC/SD(8b)(x1) NOVEMBER2010 showsthe functionalblockdiagramof the FunctionalBlockDiagramCopyright 2010 2014,TexasInstrumentsIncorporatedAM1802 ARMM icroprocessor3 SubmitDocumentationFeedbackProductFolder Links:AM1802AM1802 SPRS710E NOVEMBER2010 Contents1 SleepController(PSC)..652 (EMIFA).. SD / SDIO(MMCSD0).. (McASP).. (SPI0,SPI1).. (I2C).. (UART).. OTGC ontroller(USB0)4 [ ].. (EMAC).. (MDIO).. (RTC).. (GPIO)..162 JunctionTemperatureRange(UnlessOtherwise Noted).

5 Deviceand RecommendedPower-OnHours(POH). SupplyVoltageand (UnlessOtherwiseNoted).. PeripheralInformationand MechanicalPackagingand ContentsCopyright 2010 2014, NOVEMBER2010 REVISEDMARCH20142 RevisionHistoryNOTE:Pagenumbersfor previousrevisionsmay differfrompagenumbersin the changesmadeto the SPRS710 Ddevice-specificdatamanualto makeit an MovedTrademarksinformationfromfirst pageto withinSection7, Deviceand MovedESDSW arningto withinSection7, Deviceand DocumentationSupport. UpdatedFeatures,Applications,and Descriptionfor consistencyand Updated/Changedfootnotebeginningwith "IPD= ";addedTerminalFunctionssentence"For moredetailedinformationon "Table3-15, UniversalSerialBus (USB) Modules Updated/Changedthe capacitorvaluein USB0_VDDA12pin DESCRIPTION from"1 F" to(USB0)" F"Table3-21, UnusedUSB0 Updated/ChangedUSB0_VDDA12row text from"No Connect"to "..to an FUnusedPin Configurationsfiltercapacitor"Updated/Ch angedtitlefrom"DeviceOperatingConditions "to"Specifications" , HandlingRatings:Section5 Specifications Splithandling,ratings,and certificationsfromthe Abs Max tableand , RecommendedPower-OnHours:Noteson Recommended Updated/Changedall applicableSiliconRevisionsfrom"B" to "B/E"Power-OnHoursFigure6-12, AsynchronousMemoryReadTimingfor Addedverticallinesto showdifferencebetweenSetup,Strobe,and HoldEMIFAE lectrical/TimingFigure6-13, AsynchronousMemoryWriteTimingfor EMIFA: Addedverticallinesto showdifferencebetweenSetup,Strobe,and , DeviceNomenclature:Deviceand Development- Added"E = " 2010 2014,TexasInstrumentsIncorporatedRevisio nHistory5 SubmitDocumentationFeedbackProductFolder Links.

6 AM1802AM1802 SPRS710E NOVEMBER2010 providesan overviewof the tableshowssignificantfeaturesof the device,includingthe capacityof on-chipRAM,peripherals,and the packagetype with pin Characteristicsof the DeviceHARDWAREFEATURESAM1802 DDR2,16-bitbus width,up to 156 MHzDDR2/mDDRC ontrollerMobileDDR,16-bitbus width,up to 150 MHzAsynchronous(8/16-bitbus width)RAM,Flash,EMIFA16-bitSDRAM,NOR,NAN DF lashCardInterfaceMMCand SD cardssupported64 independentchannels,16 QDMA channels,EDMA3 Peripherals2 channelcontrollers,3 transfercontrollers4 64-BitGeneralPurpose(eachconfigurableas 2 separateNot all peripheralspinsTimers32-bittimers,one configurableas WatchDog)are availableat thesametime (for moreUART3 (eachwith RTSand CTSflow control)detail,see the DeviceSPI2 (Eachwith multiplechip selects)Configurationssection).I2C1 (Master/Slave)MultichannelAudioSerialPor t [McASP]1 (eachwith transmit/receive,FIFO buffer,16 serializers)10/100 EthernetMACwith ManagementDataI/O1 (MII or RMIII nterface) (USB0)High-SpeedOTGC ontrollerwith on-chipOTGPHYG eneral-PurposeInput/OutputPort9 banksof 16-bitSize(Bytes)168 KBRAMARM16 KBI-Cache16 KBD-CacheOn-ChipMemoryOrganization8KB RAM(VectorTable)64 KBROMADDITIONALMEMORY128 KBRAMJTAGBSDL_IDDEVIDR0 Register0x0B7D_102 FCPUF requencyMHzARM926300 MHz( )Core(V) V nominalfor 300 MHzVoltageI/O (V) V or V13 mm x 13 mm, pitch,PBGA(ZCE)Packages16 mm x 16 mm, pitch,PBGA(ZWT)ProductPreview(PP),Produc tStatus(1)AdvanceInformation(AI),PDor ProductionData(PD)(1)PRODUCTIONDATA informationis currentas of specificationsper the termsof the necessarilyincludetestingof all ARM926EJ-SRISCCPUis compatiblewith ARMS ubsystemincludesthe followingfeatures.

7 ARM926EJ-SRISC processor ARMv5 TEJ(32/16-bit)instructionset Littleendian SystemControlCo-Processor15 (CP15)6 DeviceOverviewCopyright 2010 2014, NOVEMBER2010 REVISEDMARCH2014 MMU 16 KBInstructioncache 16 KBDatacache WriteBuffer EmbeddedTraceModuleand EmbeddedTraceBuffer(ETM/ETB) ARMS ubsystemintegratesthe ARM926EJ-Sprocessoris a memberofARM9familyof targetedat multi-taskingapplicationswherefull memorymanagement,highperformance,low die size,and low powerare all 32-bitARMand 16 bit THUMB instructionsets,enablingthe usertotradeoff betweenhighperformanceand ,the ARM926EJ-Sprocessorsupportsthe ARMv5 TEJinstructionset, whichincludesfeaturesfor efficientexecutionof Javabyte codes,providingJavaperformancesimilarto Justin Time(JIT)Javainterpreter,but ARM926EJ-Sprocessorsupportsthe ARMdebugarchitectureand includeslogicto assistin bothhardwareand ARM926EJ-Sprocessorhas a Harvardarchitectureand providesacompletehigh performancesubsystem,including.

8 ARM926EJ-S integercore CP15systemcontrolcoprocessor MemoryManagementUnit (MMU) Separateinstructionand datacaches Writebuffer Separateinstructionand data(internalRAM)interfaces Separateinstructionand dataAHBbus interfaces EmbeddedTraceModuleand EmbeddedTraceBuffer(ETM/ETB)For morecompletedetailson the ARM9,referto the ARM926EJ-STechnicalReferenceManual,avail ableat ARM926EJ-Ssystemcontrolcoprocessor(CP15) is usedto configureand controlinstructionanddatacaches,MemoryMa nagementUnit (MMU),and CP15registersare programmedusingthe MRCand MCRARM instructions,whenthe ARMin a privilegedmodesuchassupervisoror singleset of two levelpagetablesstoredin mainmemoryis usedto controlthe addresstranslation,permissionchecksand memoryregionattributesfor bothdataand MMUusesasingleunifiedTranslationLookasid eBuffer(TLB)to cachethe informationheldin the : StandardARMarchitecturev4 and v5 MMUmappingsizes,domainsand accessprotectionscheme. Mappingsizesare: 1MB(sections) 64KB(largepages) 4KB (smallpages) 1KB (tiny pages) Accesspermissionsfor largepagesand smallpagescan be specifiedseparatelyfor eachquarterofthe page(subpagepermissions)Copyright 2010 2014,TexasInstrumentsIncorporatedDeviceO verview7 SubmitDocumentationFeedbackProductFolder Links:AM1802AM1802 SPRS710E NOVEMBER2010 Hardwarepagetablewalks InvalidateentireTLB,usingCP15register8 InvalidateTLB entry,selectedby MVA,usingCP15register8 Lockdownof TLB entries, WriteBufferThe size of the Instructioncacheis 16KB,Datacacheis ,the cacheshavethe followingfeatures.

9 Virtualindex,virtualtag, and addressedusingthe ModifiedVirtualAddress(MVA) Four-wayset associative,with a cacheline lengthof eightwordsper line (32-bytesper line)and withtwo dirty bits in the Dcache Dcachesupportswrite-throughand write-back(or copyback)cacheoperation,selectedby memoryregionusingthe C and B bits in the MMUtranslationtables Critical-wordfirst cacherefilling Cachelockdownregistersenablecontroloverw hichcachewaysare usedfor allocationon a line fill,providinga mechanismfor bothlockdown,and controllingcachecorruption Dcachestoresthe PhysicalAddressTAG(PA TAG)correspondingto eachDcacheentryin the TAGRAMfor use duringthe cacheline write-backs,in additionto the VirtualAddressTAGstoredin the MMUis not involvedin Dcachewrite-backoperations,removingthepo ssibilityof TLB missesrelatedto the write-backaddress. Cachemaintenanceoperationsprovideefficie ntinvalidationof, the entireDcacheor Icache,regionsofthe Dcacheor Icache,and regionsof writebufferis usedfor all writesto a noncachablebufferableregion,write-throug hregionand writemissesto a separatebufferis incorporatedin the Dcachefor holdingwrite-backforcacheline evictionsor cleaningof mainwritebufferhas 16-worddatabufferand Dcachewrite-backhas eightdatawordentriesand a (AHB)The ARMS ubsystemusesthe AHBport of the ARM926EJ-Sto connectthe ARMto the Configbus andthe employedto arbitrateaccessto the separateD-AHBand I-AHBby theConfigBus and the (ETM)and EmbeddedTraceBuffer(ETB)To supportreal-timetrace,the ARM926EJ-Sprocessorprovidesan interfaceto enableconnectionof anEmbeddedTraceMacrocell(ETM).

10 TheARM926ES-JSubsystemin the devicealsoincludestheEmbeddedTraceBuffer (ETB).The ETMconsistsof two parts: TracePort providesreal-timetracecapabilityfor the ARM9. Triggeringfacilitiesprovidetriggerresour ces,whichincludeaddressand datacomparators,counter,and devicetraceport is not pinnedout and is insteadonly connectedto the a 4KB requiredto read/interpretthe defaultthe ARMhas accessto moston and off chip memoryareas,includingEMIFA,DDR2,and theadditional128 Kbyteon chip of the on chip peripheralsare accessibleto theARMby Table3-2 for a detailedtop leveldevicememorymapthat includesthe 2010 2014, NOVEMBER2010 :Read/Writeaccessesto illegalor reservedaddressesin the AM1802 Top LevelMemoryMapStartAddressEnd AddressSizeARMMemMapEDMAMemMapMasterPeri pheralMemMap0x000000000x01 BBFFFF0x01BC00000x01BC0 FFF4 KARMETB memory0x01BC10000x01BC17FF2 KARMETBreg0x01BC18000x01BC18FF256 ARMIce Crusher0x01BC19000x01 BFFFFF0x01C000000x01C07 FFF32 KEDMA3CC0x01C080000x01C083FF1 KEDMA3TC00x01C084000x01C087FF1 KEDMA3TC10x01C088000x01C0 FFFF0x01C100000x01C10 FFF4 KPSC00x01C110000x01C11 FFF4 KPLL Controller00x01C120000x01C13 FFF0x01C140000x01C14 FFF4 KSYSCFG00x01C150000x01C1 FFFF0x01C200000x01C20 FFF4 KTimer00x01C210000x01C21 FFF4 KTimer10x01C220000x01C22 FFF4KI2C 00x01C230000x01C23 FFF4 KRTC0x01C240000x01C3 FFFF0x01C400000x01C40 FFF4 KMMC/SD00x01C410000x01C41 FFF4 KSPI 00x01C420000x01C42 FFF4 KUART00x01C430000x01 CFFFFF0x01D000000x01D00 FFF4 KMcASP0 Control0x01D010000x01D01 FFF4 KMcASP0 AFIFOCtrl0x01D020000x01D02 FFF4 KMcASP0 Data0x01D030000x01D0 BFFF0x01D0C0000x01D0 CFFF4