AN-1469PHYTER Design & Layout Guide - TI.com

1 ApplicationReportSNLA079D October2006 RevisedApril2013AN-1469 PHYTERD esign& (TP/CAT-V) (MII/RMII).. a October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013, LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013, ,fullfeatured,lowpower,10 ,forboth10 BASE-Tand100 BASE-TXEthernetprotocols,thedevicesensur ecompatibilityandinter-operabilitywithot herstandardsbasedEthernetproductsin theseapplications: HighEndPeripheralDevices IndustrialControls FactoryAutomation GeneralEmbeddedApplicationsUseofthisappl icationreport,in conjunctionwiththeproductdatasheets,andr eferencedesigns, : MDI(TwistedPair/CAT-V)Connections PowerSupplyDecoupling MACI nterface ClockConnections LEDC onnections Configuration(Strap)Connections Unused/ReservedPins PCBL ayers(stack-up) ComponentSelection/RecommendationsProduc tApplicability.

2 DP83640DP83849 CDP83848 CDP83630DP83849 IDP83848 IDP83620DP83849 IDDP83848 YBDP83849 IFDP83848 VYBDP83848 MDP83848 TDP83848 HDP83848 JDP83848 KDP83848Q-Q13 SNLA079D October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013,TexasInstrumentsIncorporatedMDI(TP/ CAT-V) (TP/CAT-V)ConnectionsThenetworkorMediumD ependentInterface(MDI)connectionis viathetransmit(TD+& TD-)andreceive(RD+& RD-) terminationnetwork,thento1:1magnetics(tr ansformer) standardCAT-VEthernetcableis , ,designsforapplicationswherea backplaneis , theAN-1519DP83848 PHYTER TransformerlessEthernetOperationApplicat ionReport(SNLA088). LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedAvoid StubsDoes Not Maintain ParallelismGround or Power (TP/CAT-V) ,1%resistors, F decouplingcapacitor,nearthePHYTERTD+/-an dRD+/-pinsandviadirectlytotheVddplane.

3 Stubsshouldbeavoidedonallsignaltraces, Withinthepairs(forexample,TD+andTD-)thet racelengthsshouldberunparalleltoeachothe randmatchedin ,avoidinganincreasein singlelayerif Stubs PCBtracelengthsshouldbekeptasshortasposs ible. Signaltracesshouldnotberunsuchthattheycr ossa A signalcrossingaplanesplitmaycauseunpredi ctablereturnpathcurrentsandwouldlikelyim pactsignalqualityaswell, October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013,TexasInstrumentsIncorporatedMDI(TP/ CAT-V) ,a solidgroundplaneis , Single-EndedStriplineImpedance- Single-EndedW= WidthofthetraceH = HeightofdielectricabovethereturnplaneT = TracethicknessEr= RelativepermittivityofthedielectricW= WidthofthetraceH = HeightofdielectricabovethereturnplaneT = TracethicknessEr= Single-EndedMicrostripImpedance- DifferentialStriplineImpedance- DifferentialW= WidthofthetraceH = HeightofdielectricabovethereturnplaneT = TracethicknessS = SpacebetweentracesEr= RelativepermittivityofthedielectricW= WidthofthetraceH = HeightofdielectricabovethereturnplaneT = TracethicknessS = spacebetweentracesEr= BobSmith terminationthrougha : Bob-SmithterminationdoesnotapplyforPower OverEthernet(PoE)applications.

4 Bob-Smith terminationis usedtoreducenoiseresultingfromcommonmode currentflows, LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013,TexasInstrumentsIncorporatedPHYC omponentOptional 0: or BeadGround PinVdd PinPCB : Usea metalshieldedRJ-45connector,andconnectth eshieldtochassisground. Usemagneticswithintegratedcommonmodechok ingdevices. Donotoverlapthecircuitandchassisgroundpl anes, (thatis,capacitorsorEMIbeads)duringsyste mlevelcertificationtestingif , ,thesameMDIsignalroutingrecommendationsd escribedin F ,thecapacitorsshouldbeplacesascloseaspos sibletothecomponentVddsupplypins, maybedesirabletoadd0 ohmresistorsin serieswithsupplypins,astheresistorpadspr ovideflexibilityifaddingEMIbeadsbecomesn ecessarytomeetsystemlevelcertificationte stingrequirements.(SeeFigure9.)It is recommendedthePCBhaveatleastonesolidgrou ndplaneandonesolidVddplanetoprovidea F October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013,TexasInstrumentsIncorporatedMACI nterface(MII/RMII) ,thePFBOUT pinshouldbetiedtothePFBIN1& 2 F tantalumcapacitorin parallelwitha F capshouldbeplacedclosetothePFBOUTpin, F capsshouldbeplacedclosetothePFBIN1andPFB IN2pins.

5 (SeeFigure10) (MII/RMII)TheMediaIndependentInterface(M II)connectsthePHYTER componenttotheMediaAccessController(MAC) .TheMACmayin factbea discretedevice,integratedintoa microprocessor, , ,thePHYTER familyofproductsalsosupportReducedMII(RM II).Foradditionalinformationonthismodeof operation,refertotheAN-1405DP83848 Single10/100Mb/sEthernetTransceiverReduc edMediaIndependentInterface(RMII)ModeApp licationReport(SNLA076). ,50ohmseriesterminationresistorsarerecom mendedforallMIIoutputsignals(includingRX CLK,TXCLK,andRXDatasignals.)NotethatDP83 849andDP83640productsprovideintegrated50 ohmsignalterminations, ,therearea longertrace, ,andif runonthesurfacelayer, a longtraceis runningnearandadjacenttoa noisysignal,theunwantedsignalscouldbecou pledin is , , , LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013, theclockinput, (orRMII mastermodein someproducts)eithera ,theuseofstandardRMII mode(notRMII mastermode)requirestheuseofa anoscillatoris used, requiredfromtheclocksource,butmayprovebe neficialin ,it seriesterminationis used, , a parallelterminationresistoris used,it (orRMII mastermodeontheDP83640),therecommendedcr ystaltouseis a 25 MHz,parallel, typicalcircuitfora.

6 :2 Crystalloadspec- 7 pF= CL(1)Theoscillatorcircuitis designedtodrivea parallelresonanceATcutcrystalwitha minimumdrivelevelof100mWanda a crystalis specifiedfora lowerdrivelevel,a currentlimitingresistorshouldbeplacedin startingpointforevaluatinganoscillatorci rcuit,if therequirementsforthecrystalarenotknown, CL1andCL2shouldbesetat33pF,andR1shouldbe setat0 October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013, k:110:LED I/O PinStrapped High,Active k:110:Conventional Input/Output Strapped HighConventional Input/Output Strapped LowLED I/O PinStrapped Low,Active (LED) ,Speed,Activity, (10kto20k) ,it is ,eventhoughtheinternalstrapresistorsarea dequateforconfiguringthedevicein mostapplications,in someapplicationswithnoisyenvironmentsit is ,in ordertoachievedualinput/outputfunctional ity,theactivestateofeachLEDoutputdriveri s dependentontheinputlogiclevelsampledduri ngpower- ,if a multifunctionLEDpinis resistivelypulledlow, ,if aninputis resistivelypulledhigh, LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013, ,atminimuma fourlayerPCBis recommendedforimplementingPHYTER componentsin ,six,andeight-layerboards, PCBit maybedesirabletoruntracesusingdifferentm ethods, , ,it maybedesirabletochangelayerstackingwhere anisolatedchassisgroundplaneis October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013, , devicemayhaveinternalpull-uporpull-downr esistors.

7 A goodpracticeis toterminateunusedCMOS inputs, ,CMOS inputscanbetieddirectlytoVddorground, ,itsconsidereda saferpracticetopullanunusedinputpinhigho rlowwitha is alsopossibletogrouptogetheradjacentunuse dinputpins,andasa grouppullthemupordownusinga Design ,selectionofcertaincomponentsis : Clocksource- oscillatororcrystal ATcut therecommendedtypeforPHYTER componentssinceATcutexhibitsthemostfrequ encystabilityovera ,a ,Pericom, LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013, 50-MHzFrequencyStability-- 50ppm0 C to70 C,1 yearaging,loadchangeRise/FallTime--6ns20 - 80%Jitter(shortterm)--25psCycle-to-cycle ,driving10pFloadJitter(longterm)--200psA ccumulativeover10 sLoadCapacitance15--pFSymmetry40-60%Logi c0--10%VDDVVDD= nominalLogic190%VDD--VVDD= 50ppm0 C to70 CFrequencyStability-- 50ppm1 5 5 ,othersmaybecompatiblefollowingtherequir ementslistedin Table4.

8 It is , , , Table5. , October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013, :1- 2%InsertionLoss-1dB1 - 100 MHzReturnLoss-16dB1 - 30 MHz- 12dB30- 60 MHz- 10dB60- 80 MHzDifferentialtoCommonRejectionRation- 30dB1 - 50 MHz- 20dB50- 150 MHzCrosstalk- 35dB30 MHz- 30dB60 MHzIsolation1, , (POR)functionanddoesnotneedtobeexplicitl yresetafterpowerup, requiredduringnormaloperation,thedevicec anberesetbya hardwareora hardwareresetis accomplishedbyapplyinga lowpulse(TTLlevel),witha durationofatleast1 ms, (similartothepower-up/resetoperation). softwareresetis accomplishedbysettingtheresetbit(bit15)o ftheBasicModeControlRegister(BMCR).Thepe riodoftimefromsettingtheresetbit,totheti mewhensoftwareresethasconcludedisapproxi mately1 msfollowingasoftwareresetbeforeallowingf urtherserialMII(MDIO/MDC) LayoutGuideSNLA079D October2006 RevisedApril2013 SubmitDocumentationFeedbackCopyright 2006 2013, conjunctionwiththisdocument,toassistin designingwithPHYTER products.

9 DP83848 CPHYTERCommTempSinglePort10/100Mb/sEther netPhyLayerTransceiver(SNOSAT2) DP83848 IIndTempSinglePort10/100Mb/sEthernetPhyL ayerTransceiver(SNLS207) DP83848 YBExtremeTempSinglePort10/100Mb/sEtherne tPhyLayerTransceiver(SNLS208) DP83848 MPHYTERMini- CommercialTemperatureSingle10/100 EthernetTransciver(SNLS227) DP83848 TPHYTERMini- IndustrialTempSingle10/100 EthernetTransceiver(SNLS228) DP83848 VYBPHYTER- ExtendedTemperatureSinglePort10/100Mb/sE thernetPhysicalLayerX-ceiver(SNLS266) DP83848 JPHYTERMiniLSCommercialTemperatureSingle Port10/100Mb/sEthernetTransceiver(SNLS25 0) DP83848 KPHYTERMiniLSIndustrialTemperatureSingle Port10/100 EthernetTransceiver(SNLS251) DP83848C/I/YBSchematic(SNLR019) DP83848C/I/YBBillofMaterials(SNLR020) DP83848M/T/HSchematic(SNLR015) DP83848M/T/HBillofMaterials(SNLR016) DP83848J/KSchematic(SNLR011) DP83848J/KBillofMaterials(SNLR012) DP83849 CPHYTERDUALC ommercialTemperatureDualPort10/100Mb/sEt hernetPhysicalLayer(SNOSAX0) DP83849 IPHYTERDUALI ndustrialTemperaturewithFlexiblePortSwit chingDualPort(SNOSAX1) DP83849 IDPHYTERDUALI ndustrialTemperaturewithFiberSupport(FX) ,DualPort10/100Mb/sEthernetPHYX-ceiver(S NOSAX2) DP83849 IFPHYTERDUALI ndustrialTemperaturewithFiberSupport(FX) andFl(SNOSAX8) DP83640 PrecisionPHYTER- IEEE 1588 PrecisionTimeProtocolTransceiver(SNOSAY8 ) AN-1519DP83848 PHYTER TransformerlessEthernetOperationApplicat ionReport(SNLA088) (For10/100Mb/soperation) PCBT raceImpedanceCalculator DifferentialImpedance15 SNLA079D October2006 RevisedApril2013AN-1469 PHYTERD esign& LayoutGuideSubmitDocumentationFeedbackCo pyright 2006 2013,TexasInstrumentsIncorporatedIMPORTA NTNOTICET exasInstrumentsIncorporatedanditssubsidi aries(TI)

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