AN Introduction to VHDL - Overview

1 AN Introduction to VHDLO verviewDinesh SharmaMicroelectronics Group, EE DepartmentIIT Bombay, MumbaiAugust 2008 Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesPart IVHDL Design Units1 Design Units in VHDL entityArchitectureComponentConfiguration Packages and Libraries2 Object and Data TypesScalar data typesComposite Data TypesDinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesAn Introduction to VHDLVHDL is a hardware description language which uses thesyntax of ADA. Like any hardware description language, it isused for many describing a modeling simulation of early performance estimation of system synthesis of fault simulation, test and verification of SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: ENTITYThe basic design element in VHDL is called an ENTITY.

2 An ENTITY represents a template for a hardware describes just the outside view of a hardware module namely its interface with other modules in terms of inputand output hardware block can be the entire design, a part of it orindeed an entire test bench .A test bench includes the circuit being designed, blockswhich apply test signals to it and those which monitor inner operation of the entity is described by anARCHITECTURE associated with SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesENTITY DECLARATIONThe declaration of an ENTITY describes the signals whichconnect this hardware to the outside. These are calledportsignals.

3 It also provides optional values of manifest are called 93entitynameisgeneric(list);port(list);e nd entityname;VHDL 87entitynameisgeneric(list);port(list);e nd name;Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesENTITY EXAMPLEVHDL 93entity flipflop isgeneric (Tprop:delaylength);port (clk, d: in bit; q: out bit);end entity flipflop;VHDL 87entity flipflopgeneric (Tprop: delaylength);port (clk, d: in bit; q: out bit);end flipflop;The entity declares port signals, their directions and signals are used by an architecture associated with SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: ARCHITECTUREAn ARCHITECTURE describes how an ENTITY operates.

4 AnARCHITECTURE is always associated with an can be multiple ARCHITECTURES associated with ARCHITECTURE can describe an entity in a structuralstyle, behavioural style or mixed language provides constructs for describing components,their interconnects and composition (structural descriptions).The language also includes signal assignments, sequentialandconcurrent statements for describing data and control flow,andfor behavioural SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesARCHITECTURE SyntaxVHDL 93architecturenameofentity-nameis(declar ations)begin(concurrent statements)end architecturename;VHDL 87architecturenameofentity-nameis(declar ations)begin(concurrent statements)end architecturename;The architecture inherits the port signals from its mustdeclare its internal signals.

5 Concurrent statements constitutingthe architecture can be placed in any SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesARCHITECTURE ExampleVHDL 93architecture simple of dff issignal ..; architecture simple;VHDL 87architecture simple of dff issignal ..; simple;Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: COMPONENTSAn ENTITY ARCHITECTURE pair actually describes a design, we might use severalinstancesof the instance of a component type may be distinguishedby using a unique , a componentinstancewith a unique instance nameis associated with a componenttype, which in turn isassociated with an ENTITY ARCHITECTURE is like saying U1 (component instance) is a D Flip Flop(componenttype) which is associated with an entity DFF(which describes its pin diagram) using architectureLS7474 (which describes its inner operation).

6 Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesComponent ExampleVHDL 93componentnameisgeneric(list);port(list );end componentname;EXAMPLE:component flipflop isgeneric (Tprop:delaylength);port (clk, d: in bit; q: out bit);end component flipflop;VHDL 87componentnamegeneric(list);port(list); end component;EXAMPLE:component flipflopgeneric (Tprop: delaylength);port (clk, d: in bit; q: out bit);end component;Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: ConfigurationStructural Descriptions describe components and component is an instance of a component type is associated withan ENTITY ARCHITECTURE architecture used can itself contain other components -whose type will then be associated with otherENTITY ARCHITECTURE configuration describes linkages between componenttypes and ENTITY ARCHITECTURE pairs.

7 It specifiesbindings for all components used in an architecture associatedwith an SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: PackagesRelated declarations and design elements like subprogramsand procedures can be placed in a package for package has a declarative part and an implementation is somewhat like entity and architecture for in a package can be referred to by description can include a use clause to incorporate thepackage in the design. Objects in the package then becomevisible to the description without having to use the dot referenceas SharmaVHDLD esign Units in VHDLO bject and Data TypesentityArchitectureComponentConfigur ationPackages and LibrariesDesign Elements in VHDL: LibrariesMany design elements such as packages, definitions and entireentity architecture pairs can be placed in a description invokes the library by first declaring it:For example,Library IEEE.

8 Objects in the Library can then be incorporated in the designbya use example,Use this example, IEEE is a library and stdlogic1164 is apackage in the SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesObject and Data Types in VHDLVHDL defines several types ofobjects. These includeconstants, variables, types of values which can be assigned to these objects arecalleddata may be assigned to example, aconstant, avariableand asignalcan all havevalues which are ofdata of objects include theirobjecttype as well as thedatatype of values that they can examplesignalEnable:BIT;Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesData Typesbit_vectorstringbitcharacterComposi teconstrainedarrayunconstrainedarrayAcce ssbooleanPhysicalFloating Levelfile_open_kindfile_open_statusScala rFileDinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesEnumeration TypeVHDL enumerationtypes allow us to define a set of values thata variable of this type can acquire.

9 For example, we can definea data type by the following declaration:typeinstris(add, sub, adc, sbb, rotl, rotr);Now a variable or a signal defined to be of type instr can onlybe assigned values enumerated above that is: add, sub, adc,sbb, rotl and actual implementation, these values may may be mapped toa 3 bit value. However, an attempt to assign, say, 010 to avariable of type instr will result in an error. Only the enumeratedvalues can be assigned to a variable of this SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesPre-defined Enumeration TypesA few enumeration types are pre-defined in the are:typebitis( 0 , 1 );typebooleanis(false, true);typeseveritylevelis(note, warning, error, failure);typefileopenkindis(readmode, writemode, appendmode);typefileopenstatusis(openok, statuserror, nameerror, modeerror);In addition to these, the character type enumerates all theASCII SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesTypes and SubTypesA signal type defined in the IEEE Library is stdlogic.

10 This is asignal which can take one of 9 possible values. It is defined by:type stdlogic is ( U , X , 0 , 1 , Z , W , L , H , - );A subtype of this kind of signal can be defined, which can takethe four values X , 0 , 1 , and Z can be defined to be a subtype of stdlogicsubtype fourvallogic is stdlogic range X to Z ;Similarly, we may want to constrain some integers to a limitedrange of values. This can be done by defining a new type:subtype bitnum is integer range 31 downto 0;Dinesh SharmaVHDLD esign Units in VHDLO bject and Data TypesScalar data typesComposite Data TypesPhysical TypesObjects which are declared to be of Physical type, carry a valueas well as a unit. These are used to represent physicalquantities such as time, resistance and Physical type defines a basic unit for the quantity and maydefine other units which are multiples of this is the only Physical type, which is pre-defined in thelanguage.