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1 Texas Instruments Incorporated Power Management Understanding output voltage limitations of DC/DC buck converters By John Tucker Low Power DC/DC Applications Introduction If the losses in the switch and catch diode are ignored, Product datasheets for DC/DC converters typically show then the duty cycle, or the ratio of ON time to the total an operating range for input and output voltages. These period, of the converter can be expressed as operating ranges may be broad and in some cases may V. overlap. It is usually not possible to derive any arbitrary D = OUT . (1). VIN. output voltage from the entire range of permissible input voltages. There are several factors that can cause this, The duty cycle is determined by the output of the error including the internal reference voltage, the minimum amplifier and the PWM ramp voltage as shown in Figure 2.

2 Controllable ON time, and the maximum duty-cycle The ON time starts on the falling edge of the PWM ramp constraints. voltage and stops when the ramp voltage equals the out- put voltage of the error amplifier. The output of the error Ideal buck-converter operation amplifier in turn is set so that the feedback portion of the Consider the theoretical, ideal buck converter shown in output voltage is equal to the internal reference voltage. Figure 1. The buck converter is used to generate a lower This closed-loop feedback system causes the output volt- output voltage from a higher DC input voltage. age to regulate at the desired level. If the output of the Figure 1. Theoretical, ideal buck converter VIN. Ramp Generator S1. Feedback L OUT. VOUT. Voltage Control Logic and + Gate Drive + R1.

3 PWM. Error Comparator S2. Amplifier COUT. +. VREF R2. Figure 2. Typical PWM waveforms at duty-cycle extremes and midpoint PWM Ramp Error Amplifier Output Duty Cycle 0% 100% 50%. 11. Analog Applications Journal 2Q 2008 High-Performance Analog Products Power Management Texas Instruments Incorporated error amplifier falls below the PWM ramp minimum, then maximum achievable output voltage. Most important of a 0% duty cycle is commanded, the converter will not these are the on resistance of the high- and low-side switch, and the output voltage is 0 V. If the error-amplifier switch elements, and the series resistance of the output output is above the PWM ramp peak, then the command- inductor. Taking these losses into account, we can now ed duty cycle is 100% and the output voltage is equal to express the duty cycle of the converter as the input voltage.

4 For error-amplifier outputs between V +I ( rDS 2 + R L ). these two extremes, the output voltage will regulate to D = OUT OUT , (6). VIN IOUT ( rDS1 rDS 2 ). VOUT = D VIN . (2). where rDS1 is the on resistance of the high-side switch, S1;. rDS2 is the on resistance of the low-side switch, S2; and RL. Practical limitations is the output-inductor series resistance. Since the loss For the ideal buck converter, any output voltage from 0 V terms are added to the numerator and subtracted from to VIN may be obtained. In actual DC/DC converter circuits, the denominator, the duty cycle increases with increasing there are practical limitations. It has been shown that the load current relative to the ideal duty cycle. This has the output voltage is proportional to the duty cycle and input effect of increasing the available minimum voltage.

5 The voltage. Given a particular input voltage, there are limita- worst-case situation for determining the minimum avail- tions that prevent the duty cycle from covering the entire able output voltage occurs when the input voltage is at its range from 0 to 100%. Most obvious is the internal refer- maximum specification, the output current is at the mini- ence voltage, VREF. Normally, a resistor divider network as mum load specification, and the switching frequency is at shown in Figure 1 is used to feed back a portion of the its maximum value. The minimum output voltage is then output voltage to the inverting terminal of the error ampli- fier. This voltage is compared to VREF; and, during steady- VOUT(min) = ton(min) fs(max) [ VIN(max) IOUT(min). state regulation, the error-amplifier output will not go (7).]

6 ( rDS1 rDS 2)] [ IOUT(min) ( rDS 2 +R L )] . below the voltage required to maintain the feedback volt- age equal to VREF. So the output voltage will be In contrast, the loss terms decrease the available maxi- R1 mum voltage, and the worst-case conditions occur at the VOUT = VREF +1 . R 2 . (3) minimum input voltage and maximum load current. Since the limiting factor, maximum duty cycle, is specified as a As R2 approaches infinity, the output voltage goes to percentage, the switching frequency is not relevant. The VREF so that the output cannot be regulated to below the maximum available output voltage is given by reference voltage. VOUT(max) = Dmax [ VIN(min) IOUT(max) ( rDS1 rDS 2 )]. There may also be constraints on the minimum control- (8). lable ON time. This may be caused by limitations in the [IOUT(max) ( rDS 2 + R L )].

7 Gate-drive circuitry or by intentional delays. This minimum controllable ON time puts an additional constraint on the Examples minimum achievable VOUT: Now we can consider a typical application and calculate VOUT(min) = ton(min) VIN fs , the minimum and maximum output voltages. For this (4). example, the input-voltage range is 20 to 28 V, and the where ton(min) is the minimum controllable ON time and fs load current required is 2 to 3 A. Table 1 shows typical is the switching frequency. datasheet characteristics of the DC/DC converter. The duty cycle may also be constrained at the upper First we need to calculate the minimum available output end. In many converters, a dead time is required to charge voltage by substituting the following parameters into the high-side switching FET gate-drive circuit.

8 Feedforward circuitry may also cause a flattening of the PWM ramp Table 1. Typical datasheet characteristics of DC/DC converter waveform as the slope of the PWM ramp is increased while the period remains constant. This will limit the maximum PARAMETER MINIMUM NOMINAL MAXIMUM. output voltage with respect to VIN. Typically, if there is a Reference Voltage (V) -- -- maximum duty-cycle limit, it will be expressed as a per- Switching Frequency (kHz) 400 500 600. centage, and the maximum output voltage will be Minimum Controllable ON Time (ns) -- 150 200. VOUT(max) = VIN Dmax . (5). Maximum Duty Cycle (%) 87 -- -- Effect of circuit losses FET rDS(on) (VIN < 10 V) (m ) -- 150 -- So far we have assumed that the components in the circuit FET rDS(on) (VIN = 10 to 30 V) (m ) -- 100 200. are ideal and lossless.

9 Of course, this is not the case. There are conduction losses associated with the compo- nents that are important in determining the minimum and 12. High-Performance Analog Products 2Q 2008 Analog Applications Journal Texas Instruments Incorporated Power Management Equation 7: ton(min) = 200 ns, fs(max) = 600 kHz, rDS1 = rDS2 ages would be V and V, respectively. The = rDS(on) = 100 m , VIN(max) = 28 V, and IOUT(min) = 2 A. nonsynchronous buck converter is capable of lower or Since the worst-case conditions occur when ton(min) and fs higher output voltages than the synchronous buck con- are at the maximum and the loss terms are at a minimum, verter under the same conditions. we use the appropriate specifications from Table 1. We also need to supply the series resistance of the output inductor.

10 Conclusion A typical value for the series resistance is 25 m , so While the ideal buck converter can theoretically provide Equation 7 can be solved as any output voltage from VIN down to 0 V, practical limita- VOUT(min) tions do exist. The output voltage cannot go below the internal reference voltage, and internal circuit operation = 200 600 [28 2 ( )] [2 ( + )] may limit the minimum ON time and maximum duty cycle. = V. Additionally, real-world circuits contain losses. These losses To calculate the maximum output voltage, we need to can act to extend the duty cycle at higher load currents substitute the following values into Equation 8: rDS1 = rDS2 and may be used to one's advantage when output-voltage = rDS(on)(max) = 200 mW, VIN(min) = 20 V, IOUT(max) = 3 A, extremes exist. Dmax = 87%, and RL = 25 mW.