Avalon® Interface Specifications - intel.com

1 Avalon Interface Specifications Updated for intel Quartus Prime Design Suite: Subscribe MNL-AVABUSREF | Send Feedback Latest document on the web: PDF | HTML. Contents Contents 1. Introduction to the Avalon Interface 4. Avalon Properties and 5. Signal Interface 5. Example: Avalon Interfaces in System 5. 2. Avalon Clock and Reset 8. Avalon Clock Sink Signal 8. Clock Sink 9. Associated Clock Interfaces ..9. Avalon Clock Source Signal Clock Source 9. Reset 10. Reset Sink Interface 10. Associated Reset Interfaces ..10. Reset Reset Source Interface 3. Avalon Memory-Mapped Introduction to Avalon Memory-Mapped 12.

2 Avalon Memory-Mapped Interface Signal 14. Interface 20. Typical Read and Write 21. Transfers Using the waitrequestAllowance 23. Read and Write Transfers with Fixed Wait-States .. 26. Pipelined 27. Burst 30. Read and Write 34. Address 36. Avalon-MM Slave 36. 4. Avalon Interrupt 38. Interrupt Avalon Interrupt Sender Signal Interrupt Sender 38. Interrupt Avalon Interrupt Receiver Signal 39. Interrupt Receiver 39. Interrupt 39. 5. Avalon Streaming 40. Terms and 41. Avalon Streaming Interface Signal 42. Signal Sequencing and Timing .. 43. Synchronous Clock 43. Avalon Interface Specifications Send Feedback 2.

3 Contents Interface Data Transfers ..44. 44. Layout .. 45. Transfer without 46. Transfer with 46. Data Transfers Using readyLatency and 46. Data Transfers Using 49. Packet Data 50. Signal Details .. 51. Protocol Details ..52. 6. Avalon Conduit Avalon Conduit Signal 54. Conduit Properties .. 54. 7. Avalon Tristate Conduit 55. Avalon Tristate Conduit Signal 57. Tristate Conduit 58. Tristate Conduit Timing ..58. A. Deprecated 60. B. Document Revision History for the Avalon Interface 61. Send Feedback Avalon Interface Specifications 3. MNL-AVABUSREF | Send Feedback 1. Introduction to the Avalon Interface Specifications Avalon interfaces simplify system design by allowing you to easily connect components in intel FPGA.

4 The Avalon Interface family defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices. Components available in Platform Designer incorporate these standard interfaces. Additionally, you can incorporate Avalon interfaces in custom components, enhancing the interoperability of designs. This specification defines all the Avalon interfaces. After reading this specification, you should understand which interfaces are appropriate for your components and which signal roles to use for particular behaviors. This specification defines the following seven interfaces: Avalon Streaming Interface (Avalon-ST) an Interface that supports the unidirectional flow of data, including multiplexed streams, packets, and DSP data.

5 Avalon Memory Mapped Interface (Avalon-MM) an address-based read/write Interface typical of master slave connections. Avalon Conduit Interface an Interface type that accommodates individual signals or groups of signals that do not fit into any of the other Avalon types. You can connect conduit interfaces inside a Platform Designer system. Alternatively, you can export them to connect to other modules in the design or to FPGA pins. Avalon Tri-State Conduit Interface (Avalon-TC) an Interface to support connections to off-chip peripherals. Multiple peripherals can share pins through signal multiplexing, reducing the pin count of the FPGA and the number of traces on the PCB.

6 Avalon Interrupt Interface an Interface that allows components to signal events to other components. Avalon Clock Interface an Interface that drives or receives clocks. Avalon Reset Interface an Interface that provides reset connectivity. A single component can include any number of these interfaces and can also include multiple instances of the same Interface type. Note: Avalon interfaces are an open standard. No license or royalty is required to develop and sell products that use or are based on Avalon interfaces. Related Information Introduction to intel FPGA IP Cores Provides general information about all intel FPGA IP cores, including parameterizing, generating, upgrading, and simulating IP cores.

7 Generating a Combined Simulator Setup Script Create simulation scripts that do not require manual updates for software or IP. version upgrades. intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, intel , the intel logo, MAX, Nios, Quartus and Stratix words and logos are trademarks of intel Corporation or its subsidiaries in the and/or other countries. intel warrants performance of its FPGA and semiconductor products to current Specifications in ISO. accordance with intel 's standard warranty, but reserves the right to make changes to any products and services 9001:2015.

8 At any time without notice. intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by intel . intel customers are advised to obtain the latest version of device Specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. 1. Introduction to the Avalon Interface Specifications MNL-AVABUSREF | Project Management Best Practices Guidelines for efficient management and portability of your project and IP files.

9 Avalon Properties and Parameters Avalon interfaces describe their behavior with properties. The specification for each Interface type defines all the Interface properties and default values. For example, the maxChannel property of Avalon-ST interfaces allows you to specify the number of channels supported by the Interface . The clockRate property of the Avalon Clock Interface provides the frequency of a clock signal. Signal Roles Each Avalon Interface defines signal roles and their behavior. Many signal roles are optional. You have the flexibility to select only the signal roles necessary to implement the required functionality.

10 For example, the Avalon-MM Interface includes optional beginbursttransfer and burstcount signal roles for components that support bursting. The Avalon-ST Interface includes the optional startofpacket and endofpacket signal roles for interfaces that support packets. Except for Avalon Conduit interfaces, each Interface may include only one signal of each signal role. Many signal roles allow active-low signals. Active-high signals are generally used in this document. Interface Timing Subsequent chapters of this document include timing information that describes transfers for individual Interface types.