Transcription of Cadence Verilog -AMS Language Reference
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5 Or its Verilog -AMS Language ReferenceJune 20053 Product Version .. 17 Related Documents .. 18 Internet Mail Address .. 19 Typographic and Syntax Conventions .. 191 Modeling Concepts.. 21 Verilog -A Language Overview .. 22 Describing a System .. 22 Analog Systems .. 23 Nodes .. 23 Conservative Systems .. 24 Signal-Flow Systems .. 24 Mixed Conservative and Signal-Flow Systems .. 25 Simulator Flow for Analog Systems .. 252 Creating Modules.. 27 Overview.
6 28 Declaring Modules .. 28 Declaring the Module Interface .. 31 Module Name .. 31 Ports .. 31 Parameters .. 34 Defining Module Analog Behavior .. 34 Defining Analog Behavior with Control Flow .. 36 Using Integration and Differentiation with Analog Signals .. 38 Using Internal Nodes in Modules .. 39 Using Internal Nodes in Behavioral Definitions .. 39 Using Internal Nodes in Higher Order Systems .. 40 ContentsCadence Verilog -AMS Language ReferenceJune 20054 Product Version Conventions.
7 43 White Space ..44 Comments ..44 Identifiers .. 44 Ordinary Identifiers .. 45 Escaped Names .. 45 Scope Rules .. 45 Numbers ..46 Integer Numbers .. 46 Real Numbers .. 46 Strings .. 474 Data Types and Objects .. 49 Integer Numbers .. 50 Real Numbers .. 50 Converting Real Numbers to Integer Numbers .. 51 Parameters .. 51 Specifying a Parameter Type .. 52 Specifying Permissible Values .. 53 Natures .. 54 Declaring a Base Nature.
8 55 Disciplines .. 57 Binding Natures with Potential and Flow .. 58 Binding Domains with Disciplines .. 59 Disciplines and Domains of Wires and Undeclared Nets .. 60 Discipline Precedence .. 60 Compatibility of Disciplines .. 60 Net Disciplines ..63 Ground Nodes .. 65 Real Nets .. 65 Named Branches .. 66 Implicit Branches .. 67 Cadence Verilog -AMS Language ReferenceJune 20055 Product Version for the Analog Block.. 69 Assignment Statements .. 69 Procedural Assignment Statements in the Analog Block.
9 70 Branch Contribution Statement .. 70 Indirect Branch Assignment Statement .. 72 Sequential Block Statement .. 73 Conditional Statement .. 74 Case Statement .. 74 Repeat Statement .. 75 While Statement .. 76 For Statement .. 76 Generate Statement .. 776 Operators for Analog Blocks .. 81 Overview of Operators .. 82 Unary Operators .. 83 Unary Reduction Operators .. 83 Binary Operators .. 85 Bitwise Operators .. 88 Ternary Operator .. 89 Operator Precedence.
10 90 Expression Short-Circuiting .. 907 Built-In Mathematical Functions .. 91 Standard Mathematical Functions .. 92 Trigonometric and Hyperbolic Functions .. 92 Controlling How Math Domain Errors Are Handled .. 93 Cadence Verilog -AMS Language ReferenceJune 20056 Product Version and Using Events.. 95 Detecting and Using Events .. 96 Initial_step Event .. 97 Final_step Event .. 98 Cross Event .. 99 Above Event .. 100 Timer Event .. 1029 Simulator Functions.
