CD4040BC, 12-Stage Ripple Carry Binary Counters …

1 CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters May 2007. CD4040BC, 12-Stage Ripple Carry Binary Counters tm CD4060BC, 14- stage Ripple Carry Binary Counters Features General Description Wide supply voltage range: to 15V The CD4060BC is a 14- stage Ripple Carry Binary counter , High noise immunity: VDD (Typ.) and the CD4040BC is a 12-Stage Ripple Carry Binary Low power TTL compatibility: Fan out of 2 driving 74L. counter . The Counters are advanced one count on the or 1 driving 74LS negative transition of each clock pulse. The Counters are reset to the zero state by a logical 1 at the reset input Medium speed operation: 8 MHz typ.

2 At VDD = 10V. independent of clock. Schmitt trigger clock input Ordering Information Order Package Number Number Package Description CD4040 BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, " Narrow CD4060 BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, " Narrow CD4060 BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, " Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering number. Connection Diagrams Pin Assignments for DIP and SOIC Pin Assignments for DIP and SOIC. CD4040BC CD4060BC.

3 Top View Top View 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters Schematic Diagrams CD4040BC. CD4060BC. 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. 2. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters CD4060B Typical Oscillator Connections RC Oscillator Crystal Oscillator 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. 3. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters Absolute Maximum Ratings(1).

4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VDD Supply Voltage to +18V. VIN Input Voltage to VDD + TS Storage Temperature Range 65 C to +150 C. PD Package Dissipation N Package 700mW. M Package 500 mW. TL Lead Temperature (Soldering, 10 seconds) 260 C.

5 Note: 1. VSS = 0V unless otherwise specified. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Rating VDD Supply Voltage +3V to +15V. VIN Input Voltage 0V to VDD. TA Operating Temperature Range 55 C to +125 C. 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. 4. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters DC Electrical Characteristics(2).

6 55 C +25 C +125 C. Symbol Parameter Conditions Min. Max. Min. Typ. Max. Min. Max. Units IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 5 5 150 A. Current VDD = 10V, VIN = VDD or VSS 10 10 300. VDD = 15V, VIN = VDD or VSS 20 20 600. VOL LOW Level VDD = 5V 0 V. Output Voltage VDD = 10V 0 VDD = 15V 0 VOH HIGH Level VDD = 5V 5 V. Output Voltage VDD = 10V 10 VDD = 15V 15 VIL LOW Level Input VDD = 5V, VO = or 2 V. Voltage VDD = 10V, VO = or 4 VDD = 15V, VO = or 6 VIH HIGH Level Input VDD = 5V, VO = or 3 V. Voltage VDD = 10V, VO = or 6 VDD = 15V, VO = or 9 IOL LOW Level VDD = 5V, VO = mA. Output Current(3) VDD = 10V, VO = VDD = 15V, VO = IOH HIGH Level VDD = 5V, VO = mA.

7 Output Current(3) VDD = 10V, VO = VDD = 15V, VO = IIN Input Current VDD = 15V, VIN = 0V 10 5. A. VDD = 15V, VIN = 15V 10 5 Note: 2. VSS = 0V unless otherwise specified. 3. Data does not apply to oscillator points 0 and 0 of CD4060BC. IOH and IOL are tested one output at a time. 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. 5. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters AC Electrical Characteristics(4). CD4040BC TA = 25 C, CL = 50pF, RL = 200k , tr = tf = 20 ns, unless otherwise noted. Symbol Parameter Conditions Min.

8 Typ. Max. Units tPHL1, tPLH1 Propagation Delay Time to Q1 VDD = 5V 250 550 ns VDD = 10V 100 210. VDD = 15V 75 150. tPHL, tPLH Interstage Propagation Delay Time VDD = 5V 150 330 ns from Qn to Qn+1 VDD = 10V 60 125. VDD = 15V 45 90. tTHL, tTLH Transition Time VDD = 5V 100 200 ns VDD = 10V 50 100. VDD = 15V 40 80. tWL, tWH Minimum Clock Pulse Width VDD = 5V 125 335 ns VDD = 10V 50 125. VDD = 15V 40 100. trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit ns VDD = 10V No Limit VDD = 15V No Limit fCL Maximum Clock Frequency VDD = 5V 4 MHz VDD = 10V 4 10. VDD = 15V 5 12. tPHL(R) Reset Propagation Delay VDD = 5V 200 450 ns VDD = 10V 100 210.

9 VDD = 15V 80 170. tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 ns VDD = 10V 100 210. VDD = 15V 80 170. CIN Average Input Capacitance Any Input 5 pF. CPD Power Dissipation Capacitance 50 pF. Note: 4. AC Parameters are guaranteed by DC correlated testing. 1987 Fairchild Semiconductor Corporation CD4040BC, DCD4060BC Rev. 6. CD4040BC, 12-Stage Ripple Carry Binary Counters CD4060BC, 14- stage Ripple Carry Binary Counters AC Electrical Characteristics(5). CD4060BC TA = 25 C, CL = 50pF, RL = 200k, tr = tf = 20 ns, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units tPHL4, tPLH4 Propagation Delay Time to Q4 VDD = 5V 550 1300 ns VDD = 10V 250 525.

10 VDD = 15V 200 400. tPHL, tPLH Interstage Propagation Delay Time VDD = 5V 150 330 ns from Qn to Qn+1 VDD = 10V 60 125. VDD = 15V 45 90. tTHL, tTLH Transition Time VDD = 5V 100 200 ns VDD = 10V 50 100. VDD = 15V 40 80. tWL, tWH Minimum Clock Pulse Width VDD = 5V 170 500 ns VDD = 10V 65 170. VDD = 15V 50 125. trCL, tfCL Maximum Clock Rise and Fall Time VDD = 5V No Limit ns VDD = 10V No Limit VDD = 15V No Limit fCL Maximum Clock Frequency VDD = 5V 1 3 MHz VDD = 10V 3 8. VDD = 15V 4 10. tPHL(R) Reset Propagation Delay VDD = 5V 200 450 ns VDD = 10V 100 210. VDD = 15V 80 170. tWH(R) Minimum Reset Pulse Width VDD = 5V 200 450 ns VDD = 10V 100 210.