Challenges in Low‐Power Analog - ISLPED

1 ChallengesinLowPowerAnalogChallenges in Low power Analog circuit design for sub 28nm cmos TechnologiesAmr FahimSthCtiSemtech CorporationInternational Symposium on Low power Electronics and DesignOutline Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog design for sub 28nm cmos DesignExamples design Examples Conclusions2 Scaling Effects Transistor cross section: Vs VdWhere: Ileakagemore in deep substrate Known as drain induced barrier lowering (DIBL) AsLscales:1)Cox 2)W (bodydoping)3 As L scales: 1) Cox 2) Wdep (body doping)Scaling Effects Leakage current scaling (W=1um) (A) ,ds( + (V)4 Scaling Effects Intrinsic Transistor Gain: Av= gm ro26 Introduction of HK/MG20222426dB)14161820Av=gm*ro ( 1A5 Ids (mA)Outline Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog design for Sub 28nm cmos DesignExamples design Examples Conclusions6 design Methodology Important Figure of merit in Analog design is the Gm/IDSratioTowards weako a ds eainversionTowards linearregion7 design Methodology Other important metrics in Analog design include: Noise: limits the minimum detectable signal (MDS)th tthliit(MDS) that the Analog circuit can process Linearity: limits the maximum possible signal that theanalogcircuitcanprocessthe Analog circuit can process dfh d Noise+Linearity define the dynamic range (DR) of the signal that the circuit can handle MDSIIPDR328 MDSIIPDR 332 design Methodology Other important metrics in Analog design include.

2 Gain(gm), Bandwidth(Ft), power consumption Define a figure of merit (FOM) to take into account dynamicrangeandbandwidthdynamic range and bandwidth This FOM describes maximum performance without regard to power consumptiong dfvIIPfFOM2log1032log10 dfvIIPfFOMnTlog1033log10 Dynamic range9 BandwidthDynamic rangeDesign Methodology FOM plot over current consumption: dfvIIPfFOMnT2log10332log10103 design Methodology Define another figure of merit (FOM2) to take into account current consumption as wellFOM2tkittthtffi ii FOM2 takes into account the current efficiency in obtaining a certain performance level dfvIIPfIgFOMnTdsm2log10332log10log102 PowerEfficiencyBandwidthDynamic Range11 design Methodology FOM2 plot over current consumption gm2212 dfvIIPfIgFOMnTdsm2log10332log10log102 design Methodology Overall design methodology:1. Generate parametric curves based on FOM or FOM2 (Ids and W are parameters)2. Choose Ids and W that meet desired specificationsspecifications13 Outline Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog design for Sub 28nm cmos DesignExamples design Examples Conclusions14 Challenges in sub 28nm CMOSff(l) Stress effects (isolation proximity): Stress = Force / Area Stressscenarios: Stress scenarios:1.

3 Force = q * E2. Stress is also induced by interface boundaries between material with different dopantdensities (adjacent NFETs or NFET/PFET boundary)boundary) Effect of stress carrier mobility shifts (current!) Mitigatebyuseofdummies&equallyspaced15 Mitigate by use of dummies & equally spaced devicesChallenges in sub 28nm cmos Diffusion proximity (well proximity) Dopant atoms scattered from adjacent photoresistScattering variability in doping profileVT variation in order to 10 s mV- Mitigate by use of dummies 16 Source: Freescale Semiconductor ( NFET) Challenges in sub 28nm cmos Device gate leakage: Gate leakage caused by quantum tunneling (A)1 , 130nm 90nm 65nm 45nm 28nmTechnology node17 Introduction of HK/MGgateoxGSfLWCi Challenges in sub 28nm cmos Gate leakage introduce low frequency pole:tunnelgfhlfbdlintunnelgateCgf 2 This creates a low frequency bound on sample and hold (S/H) circuits as well as low frequency RCfilters(suchasPLLloopfilters)18RC filters (such as PLL loop filters) Challenges in sub 28nm cmos Gate leakage causes mismatch in current mirrors:Gate leakage causes current mismatchGate leakage causes current mismatchClassical mismatch.

4 Mismatch with gate tunneling:22 IgWLAIImVT222 IiWLXIgWLAIIGIGSmVT19 Outline Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog circuit design for Sub 28nm cmos DesignExamples design Examples Conclusions20 Sub 28nm cmos circuit design Stack devices Ensure no stressed oxides during off modeUdiI/Odi Used in I/O drivers21 Sub 28nm cmos circuit design Digitally assisted Analog circuit design Use trimming/calibration loops to sense iftiiliit ithimperfections in Analog circuits mismatches, center frequency, etc. Dataconverters(DAC/ADC): Data converters (DAC/ADC): Use a higher resolution, lower frequency ADC/DAC to sense imperfections Input voltage (or digital word) is a saw tooth waveform during calibration VCO: Trim center frequency TrimLCtankamplitude22 Trim LC tank amplitudeSub 28nm cmos circuit design design techniques: Digital temperature sensor use to adjust Analog ttisettingsMultiple programmable PFETs23 Outline Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog design for Sub 28nm cmos DesignExamples design Examples Conclusions24 design Examples 9 bit SAR ADC in 28nm CMOSM etricValuePerformance Summary:Input offset voltagelib t d t t tMetricValue# at startup(DC calibration loop)fCLK900 MHzArea200um x Examplesb 10 bit current steering DAC in 28nm cmos One Slice:MetricValuePerformance Summary:MetricValue# x bitsDesign Examples VCO in 28nm cmos :PFET current mirror with embedded PSRPfSMetricValueFosc,center3 GHzPerformance Summary.

5 Tuning range800 MHzPN @ 1 MHz amplitude loopto suppress LO harmonics in LC Scaling Effects design MethodologyCh llib28 cmos Challenges in sub 28nm cmos Analog design for Sub 28nm cmos DesignExamples design Examples Conclusions28 Conclusions Scaling Effects Reviewed design MethodologyBd/IDdithdl Based on gm/ID design methodology Extended to include DR & BW29 Conclusions Challenges in sub 28nm cmos Analog designDSM effectAnalog circuit ImplicationStress effects (isolationMobility variation (BW currentStress effects (isolation proximity)Mobility variation (BW, currentmismatch, gain)Diffusion proximityVT variation (mismatch)Gate leakageNoise mismatch lowfrequencyGate leakageNoise, mismatch, low-frequency limit Analog circuit design techniquesDesign TechniqueReason / ApplicationFET kiHi hli Designexamples:DACADCVCOFET stackingHighvoltage swingDigital assist / temp sensor Trimming Analog 30 design examples: DAC, ADC, VCO))