Chapter 12 Chemical Mechanical Polishing - …

1 11 Chapter 12 Chemical MechanicalPolishing2 Objectives List applications of CMP Describe basic structure of a CMP system Describe slurries for oxide and metal CMP Describe oxide CMP process. Describe metal Polishing process. Explain the post-CMP clean23 MaterialsDesignMasksIC FabTestPackagingFinal TestThermalProcessesPhoto-lithographyEtc hPR stripImplantPR stripMetalizationCMPD ielectricdepositionWafersWafer Process Flow4 Overview Multi layer metal interconnection is required Planarization of dielectric layers is important Depth of focus (DOF) requires a flat surface toachieve high resolution The rough dielectric surface can also causeproblems in later metallization35 Tungsten CMP Tungsten has been used to form metal plugs CVD tungsten fills contact/via holes andcovers the whole wafer.

2 Need to remove the bulk tungsten film fromthe surface Fluorine based plasma etchback processes Tungsten CMP replaced etchback6P-EpiP-WaferMetal 3Al Cu AlloyIMD 3 USGM etal 4Al CuUSGS ilicon NitrideAl Cu AlloyN-WellP-WellBPSGn+n+p+p+STIUSGWAl Cu AlloyUSGM1M2Al CuUSGWIMD 1 IMD 2 TiSi2 TiTiN ARCWTi/TiNTi/TiNSidewallSpacer, USGPMD BarrierNitrideIMD 3 Passivation 1 Passivation 2 PMDCMP PSG, WCMP USG, WCMP USG, WCMP USGWCMP USGCMOS IC47 Definition of Planarization Planarization is a process that removes thesurface topologies, smoothes and flattensthe surface The degree of planarization indicates theflatness and the smoothness of the surface8 Definition of PlanarizationCompletely Conformal Film, No PlanarizationConformal and Smooth, No Planarization59 Definition of PlanarizationPartial PlanarizationGlobal Planarization10 Definition of PlanarityR PlanarityR( m)

3 Surface to > 30 Local to 10030to Planarization> 100< Surface smoothing and local planarizationcan be achieved by thermal flow oretchback Global planarization is required for thefeature size smaller than m, whichcan only be achieved by CMP12 Traditional Planarization Methods Thermal flow Sputtering etchback Photoresist etchback, Spin-on glass (SOG) etchback713 Thermal Flow A common method for dielectricplanarization, , pre-metal dielectric High temperature operation, ~1000 C PSG or BPSG reflow, become soft and startto flow due to the surface tension Limitations.

4 High temp causes excessivedopantdiffusion Higherdopantconcentration can low downtemp, however, also cause metal corrosion ifphosphorusdopantis too high (> 7 wt%)14As DepositedBPSGP-type substratep+p+N-wellP-type substrateSiO2n+n+p+p+815 After Thermal FlowBPSGP-type substratep+p+N-wellP-type substrateSiO2n+n+p+p+16 Etch Back Reflow temperature is obviously too highfor IMD can melt aluminum metal Other planarization method is needed forIMD Sputteringetchback(ion mill) and reactiveetchbackare employed917 Etch Back Argon sputtering etchback chip off dielectricat corner of the gap and taper the openings Subsequent CVD process easily fills the gapwith a reasonable planarized surface Reactive ion etchback process with CF4/O2chemistry further planarizes the surface18 CVD USGUSGAl Cu SiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO21019 Sputtering Etch Back of USGUSGAl Cu SiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO220 CVD USGUSGAl Cu SiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO21121 Reactive

5 Etch Back of USGUSGAl Cu SiBPSGP-type substratep+p+N-wellP-type substraten+n+p+p+SiO222 Photoresist Etchback PR spin-coats can baking Planarized solid thin film on wafer surface Plasma etch process with CF4/O2chemistry Oxide etched by F and PR by O Adjusting CF4/O2flow ratio allows 1:1 ofoxide to PR selectivity. Oxide could be planarized after etchback1223 After Oxide DepositedOxideMetalMetal24 Photoresist Coating and BakingOxidePhotoresistMetalMetal1325 Photoresist EtchbackOxideMetalMetal26 Photoresist EtchbackOxideMetalMetal1427 Photoresist EtchbackOxideMetalMetal28 Photoresist Etchback When F etch oxide, O will be released Higher PR etch rate due to extra oxygen PR etchback can t planarize very well After the PR etchback, dielectric filmsurface is flatter than it is just deposited.

6 In some cases, more than one PR etchbackis needed to achieve required flatness1529 SOG Etchback SOG replaces PR Advantage: some SOG can stay on the wafersurface to fill the narrow gaps PECVD USG liner and cap layer USG/SOG/USG gap fill and surfaceplanarization Sometimes, two SOG coating-curing-etchbackprocesses are used30 SOG Etchback1631 Necessity of CMP Photolithography resolutionR = K1 /NA To improve resolution,NA or DOF = K2 /2(NA)2, both approaches toimprove resolution reduceDOF DOF is about 2,083 for m and1,500 for m resolution. Here we assumedK1=K2, =248 nm(DUV)

7 , andNA= of CMP m pattern require roughness < 2000 Only CMP can achieve this planarization When feature size > m, other methodscan be used1733 Advantages of CMP Planarized surface allows higher resolution ofphotolithography process The planarized surface eliminates sidewallthinning because of poor PVD step coverage34 Metal Line Thinning Due to theDielectric StepMetal 1 Metal 2 IMD 1 PMDS idewall Thinning1835 Planarized Dielectric Surface, noMetal Line Thinning EffectMetal 1 IMD 1 PMDM etal 236 Advantages of CMP Eliminate the requirement of excessiveexposure and development to clear the thickerphotoresist regions due to the dielectric steps This improves the resolution of via hole andmetal line pattering processes Uniform thin film deposition Reduce required over etch time Reduce chance of undercut or substrate loss1937 PROver Exposure and OverDevelopmentMetal 2 Metal 2 IMD 1 PRPRN eeds more exposureand developmentPossible CD loss due to moreexposure and development38 Rough Surface.

8 Long Over EtchMetal 2 Metal 2 IMD 1 PRPRNeed a long overetch to remove2039 Flat Surface, Short Over EtchMetal 2 Metal 2 PRPRVery litter overetch is requiredIMD 140 Advantages of CMP CMP reduce defect density,improve yield Reducing the process problems in thin filmdeposition, photolithography, and etch. CMP also widens IC chip design parameters CMP can introduce defects of its own Need appropriate post-CMP cleaning2141 Applications of CMP STI formation Dielectric layer planarization PMD and IMD Tungsten plug formation Deep trench capacitor42 Applications of CMPSTICMP USGCMP PSG, WCMP PSG, WCMP USGCMP USGCMP USGCMP WCMP W2243 Applications of CMP Copper interconnection.

9 Copper is very difficult to dry etch, Dual damascene: process of choice Tungsten plug is a damascene process44 Applications of CMP It uses two dielectric etch processes, one via etch and one trench etch Metal layers are deposition into via holesand trenches. A metal CMP process removes copper andtantalum barrier layer Leave copper lines and plugs imbeddedinside the dielectric layer2345 PECVD NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGN itriden+46 PECVD USGP-EpiP-WaferN-WellP-Welln+STIp+p+USGW PSGUSGN itriden+2447 PECVD Etch Stop NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGUSGN itriden+48 PECVD USGP-EpiP-WaferN-WellP-Welln+STIp+p+USGW PSGUSGn+USG2549 Photoresist CoatingP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGUSGn+USGP hotoresist50 Via 1 Mask2651 Via 1 Mask Exposure and

10 DevelopmentP-EpiP-WaferN-WellP-Welln+STI p+p+USGWPSGUSGn+USGP hotoresist52 Etch USG, Stop on NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGUSGn+PhotoresistUSG2753 Strip PhotoresistP-EpiP-WaferN-WellP-Welln+STI p+p+USGWPSGUSGn+USG54 Photoresist CoatingP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGUSGn+USGP hotoresist2855 Metal 1 Mask56 Metal 1 Mask Exposure andDevelopmentP-EpiP-WaferN-WellP-Welln+ STIp+p+USGWPSGUSGn+USGP hotoresist2957 Etch USG and NitrideP-EpiP-WaferN-WellP-Welln+STIp+p+ USGWPSGn+PhotoresistUSGUSG58 Strip PhotoresistP-EpiP-WaferN-WellP-Welln+STI p+p+USGWPSGn+USGUSG3059 Deposit Tantalum Barrier