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Chapter 5

Chapter 5 Flip-Flops and Related DevicesGeneral digital system diagramChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-FlopsChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignNAND Latch; when SET=CLEAR=1 Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit Design0101Q = no changeNAND Latch; when pulsing the SET input to the 0 stateChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignQ = 1 NAND Latch; when pulsing the CLEAR input to the 0 stateChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignQ = 0 NAND Latch; when SET=CLEAR=0 Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit Design01111Q = Invalid000 Summary of NAND LatchChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignTerminologyChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignBouncingChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignNOR Gate LatchChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignClock Signal and Clocked Flip-FlopsChapter 5 Flip-Flops & Rel

INC222 Logic Theory and Digital Circuit Design Chapter 5 Flip-Flops & Related Devices. Flip-Flops INC222 Logic Theory and Digital Circuit Design Chapter 5 Flip-Flops & Related Devices. NAND Latch; ... Data Storage and Transfer Synchronous transfer INC222 Logic Theory and Digital Circuit Design Chapter 5 Flip-Flops & Related Devices.

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Transcription of Chapter 5

1 Chapter 5 Flip-Flops and Related DevicesGeneral digital system diagramChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-FlopsChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignNAND Latch; when SET=CLEAR=1 Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit Design0101Q = no changeNAND Latch; when pulsing the SET input to the 0 stateChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignQ = 1 NAND Latch; when pulsing the CLEAR input to the 0 stateChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignQ = 0 NAND Latch; when SET=CLEAR=0 Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit Design01111Q = Invalid000 Summary of NAND LatchChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignTerminologyChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignBouncingChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignNOR Gate LatchChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignClock Signal and Clocked Flip-FlopsChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignClocked Flip-FlopChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignSetup and Hold TimesChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit

2 DesignClocked S-C Flip-FlopChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignClocked J-K Flip-FlopChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignClocked D Flip-FlopChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignD Latch ( Transparent Latch ) Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignAsynchronous InputsChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignExp.

3 5-8 Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Setup and Hold TimeChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Propagation DelaysChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Maximum Clocking Frequency, fMAX: The highest frequency that may be applied to the CLK input of a 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Clock Pulse HIGH and LOW Times Asynchronous Active Pulse WidthChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Clock Transition Times : the clock waveform transition times (rise and fall times) should be kept very 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-Flop Timing Considerations Actual ICs 7474D flip-flop(standard TTL) 74LS112 J-K flip-flop (low-power Schottky TTL) 74C74D flip-flop(metal-gate CMOS) 74HC112 J-K flip-flop (high-speed CMOS) Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFlip-flop timing values (in nanoseconds) Chapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignTTLCMOS747474LS11274C7474HC112ts20 206025tH500 0tPHLfrom CLK to Q402420031tPLHfrom CLK to Q 251620031tPHLfrom CLR to Q402422541tPLHfrom PRE to Q251622541tw(L)CLK LOW time371510025tw(H)CLK HIGH time302010025tw(L)

4 At PRE or CLR30156025fMAXin MHz1530520 Detecting an Input SequenceChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignData storage and TransferSynchronous transferChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignAsynchronous TransferChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignParallel Data TransferChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignSerial Data Transfer :Shift RegistersChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignFrequency Division and CountingChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignState Diagram & State Table Mealy ModelINC222 Logic Theory and Digital Circuit DesignPresent StateNext State/Outputx = 0x = 1AB / 1C / 0BB / 0A / 1CA / 0C / 0 ABC0/01/10/11/00/01/0 Chapter 5 Flip-Flops & Related DevicesState Diagram & State Table Moore ModelINC222 Logic Theory and Digital Circuit DesignPresent StateNext State Outputx = 0 x = 1 ZACB0 BBC1 CBA0A/0B/1C/0010101 Chapter 5 Flip-Flops & Related DevicesChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignMicrocomputer ApplicationChapter

5 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignAnalyzing Sequential CircuitsChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignSchmitt-Trigger DevicesChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignOne-Shot (Monostable Multivibrator) Nonretriggerable One-Shot Retriggerable One-ShotChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignOne-Shot (Monostable Multivibrator) Retriggerable One-ShotChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignAstable Multivibrators Schmitt-Trigger OscillatorChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignAstable Multivibrators 555 Timer Used as an Astable MultivibratorChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit DesignChapter 5 Flip-Flops & Related DevicesINC222 Logic Theory and Digital Circuit Desig


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