Cortex-M3 Technical Reference Manual - ARM …

1 Cortex -M3.. Revision: r1p1. Technical Reference Manual Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E. Cortex-M3 . Technical Reference Manual Copyright 2005, 2006 ARM Limited. All rights reserved. Release Information Change History Date Issue Confidentiality Change 15 December 2005 A Confidential First Release 13 January 2006 B Non-Confidential Confidentiality status amended 10 May 2006 C Non-Confidential First Release for r1p0. 27 September 2006 D Non-Confidential First Release for r1p1. 13 June 2007 E Non-Confidential Minor update with no Technical changes Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

2 Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

3 Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is Final (information on a developed product). Web Address ii Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E. Contents Cortex-M3 Technical Reference Manual Preface About this Manual .. xviii Feedback .. xxiii Chapter 1 Introduction About the processor .. 1-2. Components, hierarchy, and implementation .. 1-4. Configurable options .. 1-12. Execution pipeline stages .. 1-13. Prefetch Unit .. 1-15. Branch target forwarding .. 1-16. Store buffers .. 1-19. Instruction set summary .. 1-20.

4 Product revisions .. 1-31. Chapter 2 Programmer's Model About the programmer's model .. 2-2. Privileged access and user access .. 2-3. Registers .. 2-4. Data types .. 2-10. Memory formats .. 2-11. Instruction set .. 2-13. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. iii Contents Chapter 3 System Control Summary of processor registers .. 3-2. Chapter 4 Memory Map About the memory map .. 4-2. Bit-banding .. 4-5. ROM memory table .. 4-7. Chapter 5 Exceptions About the exception model .. 5-2. Exception types .. 5-4. Exception priority .. 5-6. Privilege and stacks .. 5-9. Pre-emption .. 5-11. Tail-chaining .. 5-14. Late-arriving .. 5-15. Exit .. 5-17. Resets .. 5-20. Exception control transfer .. 5-24. Setting up multiple stacks .. 5-25. Abort model .. 5-27. Activation levels .. 5-32. Flowcharts.

5 5-34. Chapter 6 Clocking and Resets Clocking .. 6-2. Resets .. 6-4. Cortex-M3 reset modes .. 6-5. Chapter 7 Power Management About power management .. 7-2. System power management .. 7-3. Chapter 8 Nested Vectored Interrupt Controller About the NVIC .. 8-2. NVIC programmer's model .. 8-3. Level versus pulse interrupts .. 8-41. Chapter 9 Memory Protection Unit About the MPU .. 9-2. MPU programmer's model .. 9-3. MPU access permissions .. 9-13. MPU aborts .. 9-15. Updating an MPU region .. 9-16. Interrupts and updating the MPU .. 9-19. iv Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E. Contents Chapter 10 Core Debug About core debug .. 10-2. Core debug registers .. 10-3. Core debug access example .. 10-12. Using application registers in core debug .. 10-13. Chapter 11 System Debug About system debug.

6 11-2. System debug access .. 11-3. System debug programmer's model .. 11-5. FPB .. 11-6. DWT .. 11-13. ITM .. 11-29. AHB-AP .. 11-38. Chapter 12 Debug Port About the DP .. 12-2. Chapter 13 Trace Port Interface Unit About the TPIU .. 13-2. TPIU registers .. 13-8. Serial wire output connection .. 13-17. Chapter 14 Bus Interface About bus interfaces .. 14-2. AMBA 3 compliance .. 14-3. ICode bus interface .. 14-4. DCode bus interface .. 14-6. System interface .. 14-7. Unifying the code buses .. 14-9. External private peripheral interface .. 14-10. Access alignment .. 14-11. Unaligned accesses that cross regions .. 14-12. Bit-band accesses .. 14-13. Write buffer .. 14-14. Memory attributes .. 14-15. AHB timing characteristics .. 14-16. Chapter 15 Embedded Trace Macrocell About the ETM .. 15-2. Data tracing .. 15-7.

7 ETM resources .. 15-8. Trace output .. 15-11. ETM architecture .. 15-12. ETM programmer's model .. 15-16. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. v Contents Chapter 16 Embedded Trace Macrocell Interface About the ETM interface .. 16-2. CPU ETM interface port descriptions .. 16-3. Branch status interface .. 16-6. Chapter 17 AHB Trace Macrocell Interface About the AHB trace macrocell interface .. 17-2. CPU AHB trace macrocell interface port descriptions .. 17-3. Chapter 18 Instruction Timing About instruction timing .. 18-2. Processor instruction timings .. 18-3. Load-store timings .. 18-7. Chapter 19 AC Characteristics Processor timing parameters .. 19-2. Processor timing parameters .. 19-3. Appendix A Signal Descriptions Clocks .. A-2. Resets .. A-3. Miscellaneous .. A-4. Interrupt interface.

8 A-6. ICode interface .. A-7. DCode interface .. A-8. System bus interface .. A-9. Private Peripheral Bus interface .. A-10. ITM interface .. A-11. AHB-AP interface .. A-12. ETM interface .. A-13. AHB Trace Macrocell interface .. A-15. Test interface .. A-16. Glossary vi Copyright 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E. List of Tables Cortex-M3 Technical Reference Manual Change History .. ii Table 1-1 16-bit Cortex-M3 instruction summary .. 1-20. Table 1-2 32-bit Cortex-M3 instruction summary .. 1-23. Table 2-1 Application Program Status Register bit assignments .. 2-6. Table 2-2 Interrupt Program Status Register bit assignments .. 2-7. Table 2-3 Bit functions of the EPSR .. 2-8. Table 2-4 Nonsupported Thumb instructions .. 2-13. Table 2-5 Supported Thumb-2 instructions .. 2-13. Table 3-1 NVIC registers.

9 3-2. Table 3-2 Core debug registers .. 3-5. Table 3-3 Flash patch register summary .. 3-6. Table 3-4 DWT register summary .. 3-7. Table 3-5 ITM register summary .. 3-9. Table 3-6 AHB-AP register summary .. 3-10. Table 3-7 Summary of Debug interface port registers .. 3-11. Table 3-8 MPU registers .. 3-11. Table 3-9 TPIU registers .. 3-12. Table 3-10 ETM registers .. 3-13. Table 4-1 Memory interfaces .. 4-3. Table 4-2 Memory region permissions .. 4-4. Table 4-3 ROM table .. 4-7. Table 5-1 Exception types .. 5-4. Table 5-2 Priority-based actions of exceptions .. 5-6. ARM DDI 0337E Copyright 2005, 2006 ARM Limited. All rights reserved. vii List of Tables Table 5-3 Priority grouping .. 5-8. Table 5-4 Exception entry steps .. 5-12. Table 5-5 Exception exit steps .. 5-17. Table 5-6 Exception return behavior .. 5-19.

10 Table 5-7 Reset actions .. 5-20. Table 5-8 Reset boot-up behavior .. 5-21. Table 5-9 Transferring to exception processing .. 5-24. Table 5-10 Faults .. 5-28. Table 5-11 Debug faults .. 5-30. Table 5-12 Fault status and fault address registers .. 5-31. Table 5-13 Privilege and stack of different activation levels .. 5-32. Table 5-14 Exception transitions .. 5-32. Table 5-15 Exception subtype transitions .. 5-33. Table 6-1 Cortex-M3 processor clocks .. 6-2. Table 6-2 Cortex-M3 macrocell clocks .. 6-2. Table 6-3 Reset inputs .. 6-4. Table 6-4 Reset modes .. 6-5. Table 7-1 Supported sleep modes .. 7-3. Table 8-1 NVIC registers .. 8-3. Table 8-2 Interrupt Controller Type Register bit assignments .. 8-8. Table 8-3 SysTick Control and Status Register bit assignments .. 8-9. Table 8-4 SysTick Reload Value Register bit assignments.