ARM Debugger - Lauterbach

1 ARM Debugger 1 1989-2017 Lauterbach GmbHARM Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents .. ICD In-Circuit Debugger .. Processor Architecture Manuals .. ARM/CORTEX/XSCALE .. ARM Debugger ..1 Warning ..8 Introduction ..9 Brief Overview of Documents for New Users9 Demo and Start-up Scripts10 Quick Start of the JTAG Debugger ..12 Troubleshooting ..14 Communication between Debugger and Processor can not be established14 FAQ ..15 ARM15 Trace Extensions ..18 Symmetric Multiprocessing ..19 ARM Specific Implementations.

2 20 Breakpoints20 Software Breakpoints20 On-chip Breakpoints for Instructions20 On-chip Breakpoints for Data20 Hardware Breakpoints (Bus Trace only)21 Example for Standard Breakpoints22 Complex Breakpoints28 Direct ICE Breaker Access28 Example for ETM Stopping Breakpoints29 Trigger30 Virtual Terminal31 Semihosting32 SVC (SWI) Emulation Mode32 DCC Communication Mode (DCC = Debug Communication Channel)34 Runtime Measurement35 ARM Debugger 2 1989-2017 Lauterbach GmbH Coprocessors36 Access Classes38 TrustZone Technology46 Debug Permission46 Checking Debug Permission47 Checking Secure State47 Changing the Secure State from within TRACE3247 Accessing Memory47 Accessing Coprocessor CP15 Register48 Accessing Cache and TLB Contents48 Breakpoints and Vector Catch Register48 Breakpoints and Secure Modes48 Large Physical Address Extension (LPAE)

3 49 Consequence for Debugging49 Virtualization Extension, Hypervisor50 Consequence for Debugging50 Debugger Setup51 Consequence for Debugging52 Requirements for the Target Software52 MP52 ARM specific SYStem Commands ..53 Debugger about core clock53 target configuration53 Debugger according to target topology54 <parameters> describing the DebugPort 61 <parameters> describing the JTAG scan chain and signal behavior66 <parameters> describing a system level TAP Multitap 70 <parameters> configuring a CoreSight Debug Access Port DAP 72 <parameters> describing debug and trace Components 76 <parameters> which are Deprecated 86 the used CPU90 memory access (intrusive)

4 92 JTAG frequency93 the JTAG port95 memory access96 the communication with the target100 setup103 ABORTFIXDo not access memory area from 0x0 to 0x1f103 AHBHPROTS elect AHB-AP HPROT bits103 AMBAS elect AMBA bus mode103 ASYNCBREAKFIXA synchronous break bugfix104 AXIACEE nableACE enable flag of the AXI-AP104 ARM Debugger 3 1989-2017 Lauterbach GmbH AXICACHEFLAGSS elect AXI-AP CACHE bits104 AXIHPROTS elect AXI-AP HPROT bits105 BUGFIXB reakpoint bug fix105 BUGFIXV4 Asynch. break bug fix for ARM7 TDMI-S REV4106 BigEndianDefine byte order (endianness)

5 107 BOOTMODED efine boot mode107 CINVI nvalidate the cache after memory modification108 CFLUSHFLUSH the cache before step/go108 CacheParamDefine external cache108 DACRD ebugger ignores DACR access permission settings109 DAPDBGPWRUPREQF orce debug power in DAP109 DAP2 DBGPWRUPREQKeep forcing debug power in DAP2110 DAPSYSPWRUPREQF orce system power in DAP110 DAP2 SYSPWRUPREQF orce system power in DAP2111 DAPNOIRCHECKNo DAP instruction register check111 DAPREMAPR earrange DAP memory map112 DBGACKDBGACK active on Debugger memory accesses113 DBGNOPWRDWNDSCR bit 9 will be set in debug mode113 DBGUNLOCKU nlock debug register via OSLAR113 DCDIRTYB ugfix for erroneously cleared dirty bits114 DCFREEZED isable data cache linefill in debug mode114 DEBUGPORTO ptionsOptions for debug port handling114 DIAGA ctivate more log messages115 DisModeDefine disassembler mode116 DynVectorDynamic trap vector interpretation117 EnResetAllow the Debugger to drive nRESET (nSRST)

6 117 ETBFIXM arvellRead out on-chip trace data117 ETMFIXS hift data of ETM scan chain by one118 ETMFIXWOB ugfix for write-only ETM register118 ETMFIX4 Use only every fourth ETM data package118 EXECEXEC signal can be used by bustrace118 EXTBYPASSS witch off the fake TAP mechanism119 FASTBREAKDETECTIONFast core halt detection119 HRCWOVerRideEnable override mechanism119 ICEB reakerETMFIXM arvellLock on-chip breakpoints120 ICEPICKE nable/disable assertions and wait-in-reset120 ICEPICKONLYOnly ICEPick registers accessible121 IMASKASMD isable interrupts while single stepping121 IMASKHLLD isable interrupts while HLL single stepping121 INTDISD isable all interrupts122 IRQBREAKFIXB reak bugfix by using IRQ122 KEYCODED efine key code to unsecure processor122 L2 CacheL2 cache used123 ARM Debugger 4 1989-2017 Lauterbach GmbH L2 CacheBaseDefine base address of L2 cache register123 LOCKRESGo to 'Test-Logic Reset' when locked123 MACHINESPACESA ddress extension for guest OSes124 MEMORYHPROTS elect memory-AP HPROT bits125 MemStatusCheckCheck status bits during memory access125 MMUSPACESE nable space IDs125

7 MonitorHoldoffTimeDelay between monitor accesses126 MPUD ebugger ignores MPU access permission settings127 MultiplesFIXNo multiple loads/stores127 NODATANo data connected to the trace127 NOIRCHECKNo JTAG instruction register check128 NoPRCRR esetDo not cause reset by PRCR128 NoRunCheckNo check of the running state128 NoSecureFixDo not switch to secure mode129 OVERLAYE nable overlay support129 PALLADIUME xtend Debugger timeout130 PCDefine address for dummy fetches130 PROTECTIONS ends an unsecure sequence to the core130 PWRCHECKC heck power and clock131 PWRCHECKFIXC heck power and clock131 PWRDWNA llow power-down mode131 PWRDWNR ecoverMode to handle special power recovery132 PWRDWNR ecoverTimeOutTimeout for power recovery132 PWROVRS pecifies power override bit132 ResBreakHalt the core after reset133 ResetDetectionChoose method to detect a target reset134 RESetREGisterGeneric software reset134 RESTARTFIXWait after core restart135 RisingTDOT arget outputs TDO on rising edge135 ShowErrorShow data abort errors135 SOFTLONGUse 32-bit access to set breakpoint136 SOFTQUADUse 64-bit access to set breakpoint136

8 SOFTWORDUse 16-bit access to set breakpoint136 SPLITA ccess memory depending on CPSR136 StandByTraceDelaytimeTrace activation after reset137 STEPSOFTUse software breakpoints for ASM stepping137 SYSPWRUPREQF orce system power137 TIDBGENA ctivate initialization for TI derivatives138 TIETMFIXBug fix for customer specific ASIC138 TIDEMUXFIXBug fix for customer specific ASIC138 TraceStrobeDeprecated command139 TRSTA llow Debugger to drive TRST139 TURBOS peed up memory access139 ARM Debugger 5 1989-2017 Lauterbach GmbH WaitResetWait with JTAG activities after deasserting reset140 ZoneSPACESE nable symbol management for ARM zones141 ZYNQJTAGINDEPENDENTC onfigure JTAG cascading146 nRESET/nSRST on JTAG connector146 SYStem window147 ARM Specific Benchmarking Commands.

9 148 benchmarking events from event bus148 the operating mode of the benchmark counter149 BMC.<counter>.EVENTC onfigure the performance monitor150 Functions153 the measured cycles154 BMC.<counter>.RATIOSet two counters in relation154 the benchmark counter155 ARM Specific TrOnchip Commands ..156 the ICE breaker module156 data selector156 access size for data selector156 access type157 address selector158 access mode158 the use of EXTERN lines159 an address mask159 on-chip breakpoint/trace filter by ASID159 context ID comparison160 extension of address range of breakpoint161 unit A and B162 on-chip trigger settings162 bits in the vector catch register163 address selector for bus trace164 cycle type for bus trace165 TrOnchip Example165

10 Breakpoints on scalar variables166 on-chip trigger window167 CPU specific MMU Commands ..168 wise display of MMU translation table168 display of MMU translation table171 MMU table from CPU172 CPU specific SMMU Commands ..174 SMMUH ardware system MMU (SMMU)174 a new hardware system MMU178 an SMMU179 registers of an SMMU180 ARM Debugger 6 1989-2017 Lauterbach GmbH registers of context bank181 global registers of SMMU182 registers of an SMRG183 all SMMU definitions184 security state determination table185 to stream map table entries187 context bank registers188 display of SMMU page table190 the page table entries