Data Converters for High Speed CMOS Links

1 data ConvertersforHigh Speed cmos Links A PhD DissertationWilliam F. EllersickAugust 2001 Computer Systems LaboratoryDepartments of Electrical Engineering & Computer ScienceStanford UniversityiiCopyright 2001byWilliam F. Ellersick All Rights Reserved iiivAbstractThe long Links that interconnect networking and computing systems and boardsneed high throughput to avoid expensive, massively parallel connections. However, longwires suffer signal losses that increase with frequency. Digital communication techniquescan compensate for these losses, but require Analog-to-Digital and Digital-to-Analogconverters (ADCs and DACs). To understand the application of these techniques to highspeed Links , an 8 GSample/sec cmos transceiver chip is designed to explore the limits ofhigh Speed data converter transceiver chip provides a high bandwidth signal path and precision clocks,despite the large parasitic capacitances and transistor matching errors of cmos technology.

2 Small, high bandwidth sample-and-hold amplifiers are used in the ADC, andthe resulting large mismatch errors are corrected by small DACs in each ADC circuit and signal degradations such as transmitter nonlinearity, clock coupling, andstatic phase errors are also digitally corrected. Time interleaving is used to achieve8 GSa/s, and the effects of the increased data converter capacitances are reduced withbond-wire inductors. These inductors distribute the lumped parasitic capacitances at thetransceiver input and output to approximate distributed 50 transmission lines, reducingattenuation by 10dB at 4 GHz. The data Converters allow the transceiver to use digitalequalization to compensate for the 3 GHz transceiver bandwidth to allow 8 GSa/smulti-level data transmission.

3 Measured results indicate that digitally corrected dataconverters will allow digital communication techniques to be applied to high speedCMOS would like to acknowledge the guidance and expertise of Prof. Mark Horowitzand Prof. Bill Dally. Without their knowledge and the foundation of the research of theirstudents, this work would not have been possible. Ken Yang was always generous with his time and ideas, and was like a thirdadvisor to me. He designed the transmitter with his student Siamak to complete the linktransceiver. Ken Chang designed the PLL, delaying his own graduation to help megraduate. Vladimir Stojanovic tirelessly assisted with tapeout, characterization andextensive development of measurement techniques and equalization algorithms,contributing greatly to the thoroughness of this dissertation.

4 Azita Emami and Dean Liu both worked hard to help make this project bonding technician, Pauline Prather, did amazing work to support experimentationwith inductors. I d like to thank Stefanos Sidiropoulos for his insight and keen I've listed a few here, everyone in Mark's group was free with their time and ideasand made my PhD fun and easier, as were the students in Prof. Wooley s and Prof. Lee'sgroups. At Analog Devices, Kimo Tam strongly supported my efforts to complete thisdissertation, and Jesse Bankman thoroughly reviewed the d like to thank my wife Chris for her support, and Jimmy, John and Stevie forhelp with the layout of my chips and thesis is dedicated to my editor father, Fred, who unfailingly covered my compositions with arcane editing notations, always in his trademark purple for never accepting less than my best.

5 (Let It Stand)ixTable of of of of 1: 2: Transceiver Clock Transmitter Receiver 3: Receiver Sampler Design Comparator Sample/Hold Second Stage Offset Correction Offset DAC Bias Latch Output Output high Speed Receiver Reference Voltage Simulated Comparator Comparator Array 4: Transceiver Chip Transceiver Transmit DAC Inductors to Distribute Parasitic Clock Digital Phase Synthesized Logic and Transceiver Interference Multi-level Linear Decision Feedback 5: Experimental Inductors to Distribute Parasitic Timing ADC DAC Equalized Transmitter Full Transceiver 6: Serial A/D Clock of TablesTable :Simulated Comparator :ADC Performance :DAC Performance :Transceiver Performance of FiguresFigure :Pulse Distortion from Long :Equalized Pulse :Transceiver Based on DAC and :Typical :Time-Interleaved :Timing :LENOB, ENOB vs :VCO :Delay :PLL Phase Noise :Dual Loop Clock :Clock :Open Drain :Grounded Source :Passgate/Latch :Flash ADC :Offset :4-bit Flash :Time-interleaved :Sampled :Latch Impulse :StrongArm :Pass Gate :Wideband :Sample/Hold :Differential Load :Sampling :Matched Clock :Latch with Offset :Offset Correction :Offset DAC :Output Latch :Output Latch : high Speed ADC :Reference Bias :Comparator Array :Interleaved Comparator Bank :Shield :Transceiver Chip :Time Interleaved :Interleaved DAC.

6 Lumped 50 Ohm Transmission :DAC Output :a) Simulated DAC Output ) Simulated TDR of :Transceiver Block Diagram with :a) Simulated ADC Input ) Simulated TDR of ADC :Enclosed Dual Loop Clock :Transition :Synthesized Receive :Transmit :Transmit Sequence :2-PAM and 4-PAM Modulation on 18m RG59 cable (6 tap equalizers)..58 Figure :2-PAM and 4-PAM Wire Attenuation vs. :Frequency Response of Channel and :5-tap FIR :Receive :Transmit :Decision Feedback :Transceiver Die :Bond Wire :ADC Input TDR :TDR of DAC :PLL Phase Noise vs. Noise :ADC Input Offset :Offset Correction DAC Step :ADC INL After :ADC Error :ADC Frequency :ADC :ADC :Uncalibrated :Calibrated :Transceiver Clock :DAC INL and DNL vs. :DAC Noise vs. :Raw DAC :Equalized DAC :8 GSa/s Transmitter Pulse and Frequency :8 GSa/s Transceiver Pulse and Frequency :Equalized Binary and 4-Level Transceiver Schmoo :Transceiver 10-10 BER 1 IntroductionHigh Speed Links improve the size, cost and performance of systems by reducingthe number of wires needed.

7 Link data rates can be increased either by encoding more bitsin each symbol, or by running at a faster symbol rate. While running faster is generally thesimplest approach, implementation is complicated by the low pass filters inherent to wiresand semiconductors. Wires often form the dominant low pass filters in long Links , becausethe conductor resistance and the dielectric (insulation) loss both increase with capacitances and inductances also tend to form low pass filters (otherwise theymight be touted as features instead of parasitics). Low pass filters distort signal waveforms, attenuating high frequency componentswhich rounds fast edges and causing interference, as shown in Figure The nearly idealinput pulse on the left is rounded and spread out after transmission on a long wire. Theinput pulse has a strong peak, and is almost zero at adjacent sample times, while thedistorted pulse has a smaller peak, and affects the received value at several sample : Pulse Distortion from Long WireSample TimesSample Times2 Chapter 1: IntroductionThus, a train of pulses carrying digital data will interfere with each other, causing inter-symbol interference (ISI).

8 Unequalized binary data transmission fails when pulses fail toreach half-swing at the receiver, since positive and negative pulses (due to 00100 and11011 data patterns, respectively) cannot be received by comparing to a fixed (mid-swing) , wire losses and many parasitics are linear, and thus can be correctedwith adjustable high -pass filters called linear equalizers [10]. Figure shows a pulsetrain transmitted on a long wire, with the received signal on the upper right distortedbeyond reception by a simple comparator. The step response of a transmit equalizer can beseen in the first few symbol times, emphasizing the high frequency edges, then decayingto a smaller value. Because link transmitters are usually limited in voltage swing, atransmit equalizer attenuates low frequency signal components to match the highfrequency wire and parasitic losses.

9 The equalized received signal reaches the same highand low values regardless of the adjacent symbols, but has been significantly equalization becomes increasingly difficult as the parasitic attenuation example, when pulses are attenuated by a factor of 3, equalization errors must be lessthan 1/6th of the signal swing to maintain a 50% eye opening, and more complex digitalcommunication techniques become attractive. Advanced techniques such as Decision Feedback Equalization (DFE) orTomlinson precoding, multi-level modulation and adaptive interference cancellation[59][60][62] can increase performance on long Links with severe losses. However, thesetechniques all require extra resolution in the transmitters or receivers. Thus, theireffectiveness depends on the performance of very high Speed ADCs and DACs.

10 ThisFigure : Equalized Pulse TrainUnequalizedEqualizedTransmit SignalReceive Organization3thesis investigates the applicability of digital communication techniques to high speedCMOS Links by exploring the limits of ADC and DAC performance in a prototypetransceiver shown in Figure increase data rates as well as handle more wire losses, the ADC and DAC needto realize the high sample rates and bandwidths of binary transceivers while achievingmultiple bits of resolution. The data Converters need Nyquist bandwidth (half the samplingfrequency) to prevent the circuits from limiting the link performance. Roughly 4 bits ofresolution are required, with 2 bits to support multi-level signalling, and 2 more bits foradditional signal processing. Extra resolution is desirable to correct for systematicnonlinearities and interference, and to reduce quantization errors in OrganizationThe following chapters examine the performance limits of ADCs and DACs thatrun at binary transceiver rates to understand the applicability of digital communicationtechniques to high Speed Links .