R-String DAC - University of California, Berkeley

1 EECS 247 Lecture 15: data Converters 2004 Page 1EE247 Lecture 15D/A Converters D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches DAC ExamplesEECS 247 Lecture 15: data Converters 2004 Page 2R-String DAC Advantages: Simple, fast for <8-10bits Inherently monotonic Compatible with purely digital technologies Disadvantages: 2 Bresistors & 2 Bswitches for B bits High element count & larger area for B>10bits High settling time for B > 10: max= x 2 BRC*Ref:M. Pelgrom, A 10-b 50-MHz CMOS D/A converter with 75-W Buffer, JSSC, Dec.

2 1990, pp. 247 Lecture 15: data Converters 2004 Page 3R-String DACI ncluding InterpolationResistor string DACR esistor string interpolator increases resolution w/o drastic increase in 6bit DAC 3+3 Considerations:Interpolation string loading of main R stringLarge R values less loading but lower speedCan use buffersVoutEECS 247 Lecture 15: data Converters 2004 Page 4R-String DACI ncluding InterpolationUse buffers Issues: offset & speedEECS 247 Lecture 15: data Converters 2004 Page 5 Static DAC INL / DNL Errors Component matching Systematic errors Contact resistance Edge effects in capacitor arrays Process gradient Finite current source output resistance Random errors Lithography Often Gaussian distribution (central limit theorem)*Ref: C.

3 Conroy et al, Statistical Design Techniques for D/A Converters, JSSC Aug. 1989, pp. 247 Lecture 15: data Converters 2004 Page 6 Gaussian / Probability density p(x)()22x2221p(x)e2wherestandarddeviatio n:E(X) == EECS 247 Lecture 15: data Converters 2004 Page 7 Yield()2xX2 XPXxX1edx2 Xerf2 + +== = density p(x) (-X x +X)EECS 247 Lecture 15: data Converters 2004 Page 8 YieldX/ P(-X x X) [%] P(-X x X) [%] 247 Lecture 15: data Converters 2004 Page 9 Example Measurements show that the offset voltage of a batch of operational amplifiers follows a Gaussian distribution with = 2mV and = 0.

4 Fraction of opamps with |Vos| < X = 6mV: X/ = 3 % yield (we d still test before shipping!) Fraction of opamps with |Vos| < X = 400 V: X/ = yieldEECS 247 Lecture 15: data Converters 2004 Page 10 Component MismatchRR 10000100200300400No. of resistors100410081012996992988R[] Example: Two Let us assume in this example 1000 Rs measured & within +-4 OHM or + of average 1 for resistors # of devices measured & curved typically if sample size large shape is GaussianEECS 247 Lecture 15: data Converters 2004 Page 11 Component Mismatch12122dRRRRR2dRRR1 Area +== RR density p(x) 2 3 2 3 dRRTwo side-by-sideResistorsFor typical technologies & geometries1 for resistors 5%In the case of resistors isa function of areaEECS 247 Lecture 15.

5 data Converters 2004 Page 12 DNL Unit Element DACiirefRI =DNL of unit element DAC is independent of resolution! Resistor string DAC:Irefiinomrefiirefnomiinomnomnomnomno miDNLdRRRIRIDNLRRdRdRRRR = = = == =EECS 247 Lecture 15: data Converters 2004 Page 13 DNL Unit Element DACE xample:If dR/R= , what DNL spec goes into the datasheet so that of all converters meet the spec? Answer:From table: for X/ = DNL= dR/R= DNL= DNL= + LSBDNL of unit element DAC is independent of resolution! Resistor string DAC:iiDNLdRR =EECS 247 Lecture 15: data Converters 2004 Page 14 DAC INL AnalysisBAN=2B-1nnNOutput/[Lsb]Input/[Ls b]EIdealVarianceAnn 2BN-n(N-n) 2E = A-n r =n/N= A-r(A+B)= A (1-r) Variance of E: E2=(1-r)2.

6 2+ r 2. B2= (1-r). 2 Maximum @ r = , n=N/2 Max INL @ midscaleEECS 247 Lecture 15: data Converters 2004 Page 15 DAC INL Error is maximum at mid-scale (N/2): INL depends on DAC resolution and element matching While DNL= Ref: Kuboki et al, TCAS, 6 :0dnnN/2121 2 with N21 = = == = EECS 247 Lecture 15: data Converters 2004 Page 16 Untrimmed DAC INLE xample: INL= LSB = 1%B = = = = = = = + INLBINLB2log22 1221 EECS 247 Lecture 15: data Converters 2004 Page 17 Simulation Example = 1%B = 12 INL= LSB(midscale)500100015002000250030003500 4000-1012binDNL [in LSB]DNL and INL of 12 Bit converter (from converter decision thresholds) / + LSB, avg= , , range= [in LSB] / + LSB, avg= , , range= 247 Lecture 15: data Converters 2004 Page 18 Binary Weighted DAC INL same as for unit element DAC DNL depends on transition Example:0 to 1 DNL2= (d / )21 to 2 DNL2= 3 (d / )2 Consider MSB transition: 0111.

7 1000 ..4 247 Lecture 15: data Converters 2004 Page 19 MOS Device Matchingd1d2ddd1d2ddWthLdWGSthLdIII2dIII IIddVdIVVI+= = =+ Id1Id2 Current matching depends on:-Device ratio matching larger area less mismatch effect-Threshold voltage matching Larger gate-overdrive less threshold voltage mismatch effectEECS 247 Lecture 15: data Converters 2004 Page 20 Current-Switched DACs in CMOSWthLdWGSthLdddVdIVVI =+ Array Advantages:Can be very fastSmall area for <9-10bits Disadvantages:Matching depends on Vthmatching & device W/L matching256 128 64 ..1 Example: 8bit Binary WeightedEECS 247 Lecture 15: data Converters 2004 Page 21 DNL of Binary Weighted DAC()()DNLmaxBINLDNL maxmax2B12B12 DNLB2B/21121 = = + 144244314243 Worst-case transition occurs at mid-scale: Example:B = 12, = 1% DNL= LSB INL= LSB2468101214051015 DAC input code DNL2/ 2 EECS 247 Lecture 15.

8 data Converters 2004 Page 22 Simulation Example = 1%B = 12 DNL= LSB(midscale)MSB transitions clearly visible5001000150020002500300035004000-1 012binDNL [in LSB]DNL and INL of 12 Bit converter (from converter decision thresholds) / + LSB, avg= , , range= [in LSB] / + LSB, avg= , , range= 247 Lecture 15: data Converters 2004 Page 23 Another Random Run ..Now (by chance) worst DNL is result!5001000150020002500300035004000-2 -1012binDNL [in LSB]DNL and INL of 12 Bit converter (from converter decision thresholds)-1 / + LSB, avg= , , range= [in LSB] / + LSB, avg= , , range= 247 Lecture 15: data Converters 2004 Page 24 Unit Element vs Binary WeightedUnit Element DACB inary Weighted DACBINLDNLSB2212= = BSBBINLINLDNL= = 122222 Number of switched elements:Significant difference in performance and complexity!

9 EECS 247 Lecture 15: data Converters 2004 Page 25 Unit Element vs Binary WeightedExample: B=10 Unit Element DACB inary Weighted DACB2 DNL1 INLB216S21024 = ===Number of switched elements:Significant difference in performance and complexity!B2B2 DNL1 INL232216SB10 = ===EECS 247 Lecture 15: data Converters 2004 Page 26 DAC INL/DNL Summary DAC architecture has significant impact on DNL INL is independent of DAC architecture and requires element matching commensurate with overall DAC precision Results are for uncorrelated random element variations Systematic errors and correlations are usually also important Ref:Kuboki, S.

10 ; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D converters. IEEE Transactions on Circuits and Systems, , ( ), June 1982. 247 Lecture 15: data Converters 2004 Page 27 Segmented DAC Objective:compromise between unit element and binary weighted DAC Approach:B1 MSB bits unit elementsB2= B-B1 LSB bits binary weighted INL: unaffected DNL: worst case occurs when LSB DAC turns off and one more MSB DAC element turns on: same as binary weighted DAC with B2+1 bits Number of switched elements: (2B1-1) + B2 Unit Element Binary WeightedVAnalogMSB (B1 bits)(B2) 247 Lecture 15: data Converters 2004 Page 28 ComparisonExample.