DDC112: Dual Current Input 20-Bit Analog-To-Digital ...

1 ddc112 dual Current Input 20-BitANALOG-TO- digital CONVERTERFEATURES MONOLITHIC CHARGE MEASUREMENT A/DCONVERTER digital FILTER NOISE , rms INTEGRAL LINEARITY: Reading FSR HIGH PRECISION, TRUE INTEGRATING FUNC-TION PROGRAMMABLE FULL-SCALE SINGLE SUPPLY CASCADABLE OUTPUTAPPLICATIONS DIRECT PHOTOSENSOR DIGITIZATION CT SCANNER DAS INFRARED PYROMETER PRECISION PROCESS CONTROL LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSISDESCRIPTIONThe ddc112 is a dual Input , wide dynamic range, charge-digitizing Analog-To-Digital (A/D) converter with 20-Bit resolu-tion. Low-level Current output devices, such as photosensors,can be directly connected to its inputs. Charge integration iscontinuous as each Input uses two integrators; while one isbeing digitized, the other is each of its two inputs, the ddc112 combines Current -to-voltage conversion, continuous integration, programmablefull-scale range, A/D conversion, and digital filtering to achievea precision, wide dynamic range digital result.

2 In addition tothe internal programmable full-scale ranges, external integrat-ing capacitors allow an additional user-settable full-scalerange of up to provide single-supply operation, the internal A/D converterutilizes a differential Input , with the positive Input tied to the integration capacitor is reset at the beginning ofeach integration cycle, the capacitor charges to VREF. Thischarge is removed in proportion to the Input Current . At theend of the integration cycle, the remaining voltage is com-pared to high-speed serial shift register which holds the result ofthe last conversion can be configured to allow multiple DDC112units to be cascaded, minimizing interconnections. TheDDC112 is available in an SO-28 or TQFP-32 package and isoffered in two performance by US Patent #5841310 DualSwitchedIntegratorDualSwitchedIntegr ator ModulatorDigitalFilterControlDigitalInpu t/OutputDVALIDDXMITDOUTDINDCLKRANGE2 RANGE1 RANGE0 TESTCONVCLKCAP1 ACAP1 ACAP1 BCAP1 BCAP2 ACAP2 ACAP2 BCAP2 BIN2IN1 VREFDGNDDVDDAGNDAVDDCHANNEL 1 CHANNEL 2 SBAS085B JANUARY 2000 REVISED OCTOBER 2004 ddc112 ddc112 DATA information is Current as of publication conform to specifications per the terms of Texas Instrumentsstandard warranty.

3 Production processing does not necessarily includetesting of all 2000-2004, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data trademarks are the property of their respective to to +6 VAVDD to AGND .. to +6 VDVDD to DGND .. to +6 VAGND to DGND .. Voltage to AGND .. to AVDD + Input Voltage to DGND .. to DVDD + Output Voltage to DGND .. to DVDD + Power Dissipation .. (TJMAX TA)/ JAMaximum Junction Temperature (TJMAX) .. +150 CThermal Resistance, SO, +150 C/WThermal Resistance, TQFP, +100 C/WLead Temperature (soldering, 10s).

4 +300 CNOTE: (1) Stresses above those listed under Absolute Maximum Ratings maycause permanent damage to the device. Exposure to absolute maximumconditions for extended periods may affect device MAXIMUM RATINGS(1)PACKAGE/ORDERING INFORMATION(1)MAXIMUMSPECIFICATIONINTEGR ALTEMPERATUREPACKAGEORDERINGTRANSPORTPRO DUCTLINEARITY ERRORRANGEPACKAGE-LEADDESIGNATORNUMBER(2 )MEDIADDC112U Reading FSR 40 C to +85 CSO-28 DWDDC112 URails"""""DDC112U/1 KTape and ReelDDC112UK Reading FSR0 C to +70 CSO-28 DWDDC112 UKRails"""""DDC112UK/1 KTape and ReelDDC112Y Reading FSR 40 C to +85 CTQFP-32 PJTDDC112Y/250 Tape and Reel"""""DDC112Y/2 KTape and ReelDDC112YK Reading FSR0 C to +70 CTQFP-32 PJTDDC112YK/250 Tape and Reel"""""DDC112YK/2 KTape and ReelNOTES: (1) For the most Current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

5 (2) Models with a slash(/) are available only in Tape and Reel in the quantities indicated (/1K indicates 1000 devices per reel). Ordering 1000 pieces of DDC112U/1K will get a single 1000-piece Tape and SENSITIVITYThis integrated circuit can be damaged by ESD. Texas Instru-ments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage can range from subtle performance degradationto complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametricchanges could cause the device not to meet its CHARACTERISTICSAt TA = +25 C, AVDD = DVDD = +5V, DDC112U, Y: TINT = 500 s, CLK = 10 MHz, DDC112UK, YK: TINT = s, CLK = 15 MHz, VREF = + , continuous modeoperation, and internal integration capacitors, unless otherwise noted.

6 Specifications same as DDC112U, : (1) Input is less than 1% of full scale. (2) CSENSOR is the capacitance seen at the ddc112 inputs from wiring, photodiode, etc. (3) FSR is Full-Scale Range.(4) A best-fit line is used in measuring linearity. (5) Matching between side A and side B, not Input 1 to Input 2. (6) Voltage produced by the ddc112 at its Input whichis applied to the sensor. (7) Range drift does not include external reference drift. (8) Input reference Current decreases with increasing TINT (see the Voltage Referencesection). (9) Data format is Straight Binary with a small offset (see the Data Retrieval section). (10) Ensured by design but not production , YDDC112UK, YKPARAMETERCONDITIONSMINTYPMAXMINTYPMAXU NITSANALOG INPUTSE xternal, Positive Full-ScaleRange 0 CEXT = 250pF1000 pCInternal, Positive Full-ScaleRange pCRange 295100105 pCRange pCRange 4190200210 pCRange pCRange 6285300315 pCRange pCNegative Full-Scale Input of Positive FS pCDYNAMIC CHARACTERISTICSC onversion Rate23kHzIntegration Time, TINTC ontinuous Mode5001,000, sIntegration Time, TINTNon-Continuous Mode50 sSystem Clock Input (CLK)11012 15 MHzData Clock (DCLK)1215 MHzACCURACYN oise, Low-Level Current Input (1) CSENSOR(2) = 0pF, Range 5 (250pC) ppm of FSR(3), rmsCSENSOR = 25pF, Range 5 (250pC) ppm of FSR, rmsCSENSOR = 50pF, Range 5 (250pC)

7 7ppm of FSR, rmsDifferential Linearity Error Reading (max) Integral Linearity Error(4) Reading (typ) Reading (max) No Missing Codes20 BitsInput Bias CurrentTA = +25 pARange ErrorRange 5 (250pC)5 % of FSRR ange Error Match(5)All % of FSRR ange Sensitivity to VREFVREF = :1 Offset ErrorRange 5, (250pC) 200 600ppm of FSRO ffset Error Match(5) 100 ppm of FSRDC Bias Voltage(6) ( Input VOS) 2 mVPower-Supply Rejection Ratio 25 200 ppm of FSR/VInternal Test Signal13 pCInternal Test Accuracy 10 %PERFORMANCE OVER TEMPERATUREO ffset Drift 3(10)ppm of FSR/ COffset Drift Stability (10)ppm of FSR/minuteDC Bias Voltage DriftApplied to Sensor Input3 1 V/ CInput Bias Current Drift+25 C to +45 (10) pA/ CInput Bias CurrentTA = +75 C250(10) pARange Drift(7)Range 5 (250pC)2502550(10)ppm/ CRange Drift Match(5)Range 5 (250pC) ppm/ VInput Current (8)TINT = 500 s150225275 ADIGITAL Input /OUTPUTL ogic + VVIL + VVOHIOH = 500 VVOLIOL = 500 VInput Current , IIN 10+10 AData Format(9)

8 Straight Binary POWER-SUPPLY REQUIREMENTSP ower-Supply VoltageAVDD and VSupply CurrentAnalog CurrentAVDD = + CurrentDVDD = + Power Dissipation8010085130mWTEMPERATURE RANGES pecified Performance 40+850+70 CStorage 60+100 DESCRIPTIONSPINLABELDESCRIPTION1IN1 Input 1: analog Input for Integrators 1A and 1B. Theintegrator that is active is set by the CONV Ground3 CAP1 BExternal Capacitor for Integrator 1B4 CAP1 BExternal Capacitor for Integrator 1B5 CAP1 AExternal Capacitor for Integrator 1A6 CAP1 AExternal Capacitor for Integrator 1A7 AVDDA nalog Supply, +5V Nominal8 TESTTest Control Input . When HIGH, a test charge is appliedto the A or B integrators on the next CONV which side of the integrator is connected toinput. In continuous mode; CONV HIGH side A isintegrating, CONV LOW side B is integrating.

9 CONV must be synchronized with CLK (see Figure 2).10 CLKS ystem Clock Input , 10 MHz Nominal11 DCLKS erial Data Clock Input . This Input operates the serial I/O shift Data Transmit Enable Input . When LOW, thisinput enables the internal serial shift digital Input . Used to cascade multiple Supply, +5V Nominal15 DGNDD igital Ground16 DOUTS erial Data Output, Hi-Z when DXMIT is HIGH17 DVALIDData Valid Output. A LOW value indicates valid data isavailable in the serial I/O Range Control Input 0 (least significant bit)19 RANGE1 Range Control Input 120 RANGE2 Range Control Input 2 (most significant bit)21 AGNDA nalog Ground22 VREFE xternal Reference Input , + Nominal23 CAP2 AExternal Capacitor for Integrator 2A24 CAP2 AExternal Capacitor for Integrator 2A25 CAP2 BExternal Capacitor for Integrator 2B26 CAP2 BExternal Capacitor for Integrator 2B27 AGNDA nalog Ground28IN2 Input 2: analog Input for Integrators 2A and 2B.

10 Theintegrator that is active is set by the CONV CONFIGURATIONTop ViewSO1234567891011121314282726252423222 1201918171615IN2 AGNDCAP2 BCAP2 BCAP2 ACAP2 AVREFAGNDRANGE2 (MSB)RANGE1 RANGE0 (LSB) (MSB)RANGE1123456782423222120191817 ddc112 YCAP1 BCAP1 BAGNDIN1IN2 AGNDCAP2 BCAP2B3231302928272625 DCLKDXMITDINDVDDDGNDDOUTDVALIDRANGE0 (LSB)910111213141516 PIN CONFIGURATIONTop ViewTQFPPIN DESCRIPTIONSPINLABELDESCRIPTION1 CAP1 AExternal Capacitor for Integrator 1A2 CAP1 AExternal Capacitor for Integrator 1A3 AVDDA nalog Supply, +5V Nominal4 NCNo Connection5 NCNo Connection6 TESTTest Control Input . When HIGH, a test charge isapplied to the A or B integrators on the next which side of the integrator is connected toinput. In continuous mode; CONV HIGH side A isintegrating, CONV LOW side B is integrating CONV must be synchronized with CLK (see text).