DDR2 SDRAM Device Operating & Timing Diagram

1 Device OperationsDDR2 SDRAMDDR2 SDRAM Device Operating & Timing DiagramDevice OperationsDDR2 SDRAMSelfIdleSettingEMRSBankPrechargingP owerWritingACTRDAReadSRFREFCKEL(E)MRSCKE HCKEH CKELW riteAutomatic SequenceCommand SequenceRDAWRAReadPR, PRAPRR efreshingRefreshingDownPowerDownActivewi th RDAR eadingwithWRAA ctivePrechargeReadingWritingPR(A) = Precharge (All)(E)MRS = (Extended) Mode Register SetSRF = Enter Self RefreshREF = RefreshCKEL = CKE low, enter Power DownCKEH = CKE high, exit Power Down, exit Self RefreshACT = ActivateWR(A) = Write (with Autoprecharge)RD(A) = Read (with Autoprecharge)Simplified State DiagramFunctional DescriptionAll banks prechargedActivatingCKEHReadWrite CKELMRSCKELS equenceInitializationOCDcalibrationCKEL CKELCKELA utoprechargeAutoprechargePR, PRAPR, PRAW riteWRANote : Use caution with this Diagram . It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/exit - among other things - are not captured in full detail.

2 Device OperationsDDR2 SDRAMB asic Functionality Read and write accesses to the ddr2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to deter-mine if the auto precharge command is to be issued. Prior to normal operation, the ddr2 SDRAM must be initialized. The following sections provide detailed information covering Device initialization, register definition, command descriptions and Device up and InitializationDDR2 SDRAMs must be powered up and initialized in a predefined manner.

3 Operational procedures other than those specified may result in undefined operation. Power-up and Initialization Sequence1. The following sequence is required for POWER UP and power and attempt to maintain CKE below *VDDQ and ODT*1 at a low state (all other inputs may be undefined.) The power voltage ramps are without any slope reversal, ramp time must be no greater than 200mS; and during the ramp, VDD>VDDL>VDDQ and VDD-VDDQ< VDD*2, VDDL*2 and VDDQ are driven from a single power converter output, AND- VTT is limited to V max, AND- Vref tracks Apply VDD*2 before or at the same time as Apply VDDL*2 before or at the same time as Apply VDDQ before or at the same time as VTT & least one of these two sets of conditions must be Start clock and maintain stable For the minimum of 200 s after stable power and clock(CK, CK), then apply NOP or deselect & take CKE Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns Issue EMRS(2) command.

4 (To issue EMRS(2) command, provide Low to BA0, High to BA1.)6. Issue EMRS(3) command. (To issue EMRS(3) command, provide High to BA0 and BA1.)7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1-2 and A13-A15.)8. Issue a Mode Register Set command for DLL reset *2. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-1) 9. Issue precharge all Issue 2 or more auto-refresh Issue a mode register set command with low to A8 to initialize Device operation. ( to program Operating parameters without resetting the DLL)12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).If OCD calibration is not used, EMRS OCD Default command (A9=A8= A7=1) followed by EMRS OCD Calibration Mode Exit command (A9=A8=A7=0) must be issued with other Operating parameters of The ddr2 SDRAM is now ready for normal operation.*1) To guarantee ODT off, VREF must be valid and a low level must be applied to the ODT pin.

5 *2) If DC voltage level of VDDL or VDD is intentionally changed during normal operation, (for example, for the purpose of VDD corner test, or power saving) DLL Reset must be OperationsDDR2 SDRAMI nitialization Sequence after Power Up/CKCKCKEC ommandPREALLPREALLEMRSMRSREFREFMRSEMRSEM RSANYCMDDLLENABLEDLLRESETOCDD efaultOCDCAL. MODEEXITF ollow OCDF lowchart400nstRFCtRFCtRPtRPtMRDtMRDtMRDt OITmin. 200 CycleNOPODTtCLtCHtIStISProgramming the Mode and Extended Mode RegistersFor application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(WR) are user defined variables and must be pro-grammed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance, additive CAS latency, ODT(On Die Termina-tion), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register(MR) or Extended Mode Registers(EMR(#)) can be altered by re-executing the MRS and EMRS Commands.

6 If the user chooses to modify only a subset of the MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued. MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be executed any time after power-up without affecting array OperationsDDR2 SDRAMDDR2 SDRAM Mode Register Set (MRS)The mode register stores the data for controlling the various Operating modes of ddr2 SDRAM . It controls CAS latency, burst length, burst sequence, testmode, DLL reset, WR and various vendor specific options to make ddr2 SDRAM useful for various applications. The default value of the mode registeris not defined, therefore the mode register must be written after power-up for proper operation. The mode register is written by asserting low on CS, RAS,CAS, WE, BA0 and BA1, while controlling the state of address pins A0 ~ A15. The ddr2 SDRAM should be in all bank precharge with CKE already highprior to writing into the mode register.

7 The mode register set command cycle time (tMRD) is required to complete the write operation to the mode mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are inthe precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options of 4 and 8bit burst lengths. The burst length decodes are compatible with DDR SDRAM . Burst address sequence type is defined by A3, CAS latency is defined byA4 ~ A6. The ddr2 doesn t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRSoperation. Write recovery time WR is defined by A9 ~ A11. Refer to the table for specific codes. Address FieldCAS LatencyA6A5A4 Latency000 Reserved001 Reserved0102 (Optional)0113 (speed bin determined)*10041015 (speed bin determined)*1106 (speed bin determined)*111 Reserved* speed bin determined= Not required on all speed binA7 mode0 Normal1 TestA3 Burst Type0 Sequential1 InterleaveA8 DLL Reset0No1 YesMode RegisterWrite recovery for autoprechargeA11A10A9WR(cycles)000 Reserved001 2010 3011 4100 5101 6110 Reserved111 ReservedBurst LengthA2A1A0BL010 4011 8*1 : A13 is reserved for future use and must be programmed to 0 when setting the mode and A14 are not used for 512Mb, but used for 1Gb and 2Gb ddr2 SDRAMs.

8 A15 is reserved for future usage.*2 : WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value. This is also used with tRP to determine mode00 MRS01 EMRS(1)10 EMRS(2): Reserved11 EMRS(3): ReservedDDR2-400 ddr2 -533 ddr2 -667 ddr2 -800*2A12 Active power down exit time0 Fast exit(use tXARD)1 Slow exit(use tXARDS)BA2*1BA1BA0 A15*1~A13A12A11A10A9A8A7A6A5A4A3A2A1A0 0*100 0*1 PDWRDLLTMCAS LatencyBTBurst LengthDevice OperationsDDR2 SDRAMDDR2 SDRAM Extended Mode Register Set EMRS(1)The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. Thedefault value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation.

9 Theextended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0, while controlling the states of address pins A0 ~ A13. TheDDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. The mode register set commandcycle time (tMRD) must be satisfied to complete the write operation to the extended mode register. Extended Mode register contents can be changed usingthe same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable ordisable. A1 is used for enabling a half strength data-output driver. A3~A5 determines the additive latency, A2 and A6 are used for ODT value selection,A7~A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS Enable/DisableThe DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after havingthe DLL disabled.

10 The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh time the DLL is enabled (and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for the internalclock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK (2)The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extendedmode register(2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting low on CS, RAS, CAS, WE,high on BA1 and low on BA0, while controlling the ststes of address pins A0 ~ A15. The ddr2 SDRAM should be in all bank precharge with CKE alreadyhigh prior to writing into the extended mode register(2). The mode register set command cycle time (tMRD) must be satisfied to complete the write operationto the extended mode register(2).