DDR3 SDRAM Specification - Samsung us

1 Rev. February 2009 1 of 35 DDR3 SDRAMU nbuffered SoDIMMDDR3 SDRAM Specification204pin Unbuffered SODIMM based on 1Gb E-die64-bit Non-ECC78/96 FBGA with Lead-Free & Halogen-Free(RoHS compliant)* Samsung Electronics reserves the right to change products or Specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO Samsung PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN Samsung PRODUCTS OR TECHNOL-OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY For updates or additional information about Samsung products, contact your nearest Samsung Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

2 Rev. February 2009 2 of 35 DDR3 SDRAMU nbuffered DDR3 Unbuffered SoDIMM Ordering Information .. Key Features .. Address Configuration .. x64 DIMM Pin Configurations (Front side/Back Side) .. Pin Description .. Input/Output Functional Description .. Function Block Diagram: .. 1GB, 128Mx64 Module (Populated as 2 ranks of x16 DDR3 SDRAMs) .. 1GB, 128Mx64 Module(Populated as 1 rank of x8 DDR3 SDRAMs) .. 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs) .. Absolute Maximum Ratings .. Absolute Maximum DC Ratings .. DRAM Component Operating Temperature Range .. AC & DC Operating Conditions .. Recommended DC Operating Conditions (SSTL-15) .. AC & DC Input Measurement Levels .. AC & DC Logic Input Levels for Single-ended Signals .. VREF Tolerances.. AC and DC Logic Input Levels for differential Signals.

3 differential Signals Definition .. differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) .. Single-ended Requirements for differential Signals .. differential Input Cross Point Voltage .. Slew Rate Definition for Single Ended Input Signals .. Slew rate definition for differential Input Signals .. AC & DC Output Measurement Levels .. Single Ended AC and DC Output Levels .. differential AC and DC Output Levels .. Single-ended Output Slew Rate .. differential Output Slew Rate .. IDD Specification definition .. IDD SPEC Table .. Input/Output Capacitance .. 2Rx16 1GB SoDIMM .. 1Rx8 1GB SoDIMM .. 2Rx8 2GB SoDIMM .. Electrical Characteristics and AC timing .. Refresh Parameters by Device Density .. Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .. Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin.

4 Speed Bin Table Notes ..27 Table ContentsRev. February 2009 3 of 35 DDR3 SDRAMU nbuffered Timing Parameters for DDR3-1066 and DDR3-1333 .. Jitter Notes .. Timing Parameter Notes .. Physical Dimensions : .. 64 Mbx16 based 128Mx64 Module (2 Ranks) .. 128 Mbx16 based 128Mx64 Module (1 Rank) .. 128 Mbx8 based 256MX64 Module (2 Ranks) ..35 Rev. February 2009 4 of 35 DDR3 SDRAMU nbuffered SoDIMMR evision - First ReleaseRev. February 2009 5 of 35 DDR3 SDRAMU nbuffered DDR3 Unbuffered SoDIMM Ordering InformationNote :* ## : F8 / H9** F8 : 1066 Mbps 7-7-7, H9 : 1333 Mbps Key Features JEDEC standard Power Supply VDDQ = 400 MHz fCK for 800Mb/sec/pin, 533 MHz fCK for 1066Mb/sec/pin, 667 MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 6,7,8,9 Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333) 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] Bi-directional differential Data Strobe Internal(self) calibration.

5 Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin Average Refresh Period at lower than TCASE 85 C, at 85 C < TCASE < 95 C Asynchronous Address ConfigurationPart NumberDensityOrganizationComponent CompositionNumber of RankHeightM471B2874EH1-CF8/H91GB128Mx646 4Mx16(K4B1G1646E-HC##)*8230mmM471B2873EH 1-CF8/H91GB128Mx64128Mx8(K4B1G0846E-HC## )*8130mmM471B5673EH1-CF8/H92GB256Mx64128 Mx8(K4B1G0846E-HC##)*16230mmSpeedDDR3-10 66 DDR3-1333 Unit7-7-79-9-9tCK(min) Latency79tCKtRCD(min) (min) (min) (min) AddressColumn AddressBank AddressAuto Precharge64x16(1Gb) based ModuleA0-A12A0-A9BA0-BA2A10/AP128x8(1Gb) based ModuleA0-A13A0-A9BA0-BA2A10/APRev. February 2009 6 of 35 DDR3 SDRAMU nbuffered x64 DIMM Pin Configurations (Front side/Back Side)Note :1. NC = No Connect, NU = Not Usable, RFU = Reserved Future Use2.

6 TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination ELECTRONICS CO., Ltd. reserves the right to change products and specifications without NC 78A153147DQ40148DQ4511 DM0 12 DQS079 BA2 80A143149DQ41150 VSS13 VSS14 VSS81 VDD82 VDD151 VSS152 DQS515DQ216DQ683A12/BC84A11153DM5154 DQS517DQ318DQ785A986A7155 VSS156 VSS19 VSS20 VSS87 VDD88 VDD157DQ42158DQ4621DQ822DQ1289A890A6159D Q43160DQ4723DQ924DQ1391A592A4161 VSS162 VSS25 VSS26 VSS93 VDD94 VDD163DQ48164DQ5227 DQS128DM195A396A2165DQ49166DQ5329 DQS130 RESET97A198A0167 VSS168 VSS31 VSS32 VSS99 VDD100 VDD169 DQS6170DM633DQ1034DQ14101CK0102CK1171 DQS6172 VSS35DQ1136DQ15103CK0104CK1173 VSS174DQ5437 VSS38 VSS105 VDD106 VDD175DQ50176DQ5539DQ1640DQ20107A10/AP10 8BA1177DQ51178 VSS41DQ1742DQ21109BA0110 RAS179 VSS180DQ6043 VSS44 VSS111 VDD112 VDD181DQ56182DQ6145 DQS246 DM2113WE114S0183DQ57184 VSS47 DQS248 VSS115 CAS116 ODT0185 VSS186 DQS749 VSS50DQ22117 VDD118

7 VDD187DM7188 DQS750DQ1852DQ23119A133120 ODT1189 VSS190 VSS53DQ1954 VSS121S1 122 NC 191DQ58192DQ6255 VSS56DQ28123 VDD124 VDD193DQ59194DQ6357DQ2458DQ29125 TEST126 VREFCA195 VSS196 VSS59DQ2560 VSS127 VSS128 VSS197SA0198NC61 VSS62 DQS3129DQ32130DQ36199 VDDSPD200 SDA63DM364 DQS3131DQ33132DQ37201SA1202 SCL65 VSS66 VSS133 VSS134 VSS203 VTT204 VTT67DQ2668DQ30135 DQS4136 DM469DQ2770DQ31137 DQS4138 VSSRev. February 2009 7 of 35 DDR3 SDRAMU nbuffered Pin Description *The VDD and VDDQ pins are tied common to a single power-plane on these NameDescriptionNumberPin NameDescriptionNumberCK0, CK1 Clock Inputs, positive line2DQ0-DQ63 Data Input/Output64CK0, CK1 Clock Inputs, negative line2DM0-DM7 Data Masks/ Data strobes,Termination data strobes8 CKE0, CKE1 Clock Enables2 DQS0-DQS7 Data strobes8 RASRow Address Strobe1 DQS0-DQS7 Data strobes complement8 CASC olumn Address Strobe1 RESETR eset Pin1 WEWrite Enable1 TESTL ogic Analyzer specific test pin (No connect on SODIMM)

8 1S0, S1 Chip Selects2 VDDCore and I/O Power18A0-A9, A11, A13-A15 Address Inputs14 VSSG round52A10/APAddress Input/Autoprecharge1 VREFDQVREFCAI nput/Output Reference2A12/BCAddress Input/Burst chop1 VDDSPDSPD and Temp sensor Power1BA0-BA2 SDRAM Bank Addresses3 VTTT ermination Voltage2 ODT0, ODT1On-die termination control2 NCReserved for future use3 SCLS erial Presence Detect (SPD) Clock Input1 Total204 SDASPD Data Input/Output1SA0-SA1 SPD Address2 Rev. February 2009 8 of 35 DDR3 SDRAMU nbuffered Input/Output Functional DescriptionSymbolTypeFunctionCK0-CK1CK0- CK1 InputThe system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-tions is synchronized to the input the DDR3 SDRAM CK signal when high and deactivates the CK signal when low.

9 By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh the associated DDR3 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. RAS, CAS, WEInputWhen sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define the operation to be executed by the which DDR3 SDRAM internal bank of eight is on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode ,A10/AP,A11A12/BCA13-A15 InputDuring a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK.

10 In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to (BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be performed (HIGH, no burst chop; LOW, burst chopped)DQ0-DQ63I/O Data Input/Output data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high.