Design Compiler UG: 1. Introduction to Design …

1 Compiler user Guide1 Introduction to Design Compiler1 Design Compiler is the core of the Synopsys synthesis softwareproducts. It provides constraint-driven optimization and supports awide range of Design styles. The Design Compiler tools synthesizeyour HDL description into a technology-dependent, gate-level Compiler optimizes combinational or sequential designs forspeed, area, and power, and supports both flat and 1-1 Design Compiler OverviewVHDL SourceVerilog SourceOther Input FormatsVHDL CompilerHDL CompilercompileDesign CompilerMapped,Technology-Dependent Compiler user GuideDesign Compiler provides links to electronic Design automation (EDA)

2 Tools, such as place and route tools, and post layout resynthesistechniques, such as in-place optimization. These EDA tool linksenable sharing of information (such as forward-directed constraintsand delays) between Design Compiler and external chapter includes the following sections: Design Compiler Products user Interfaces Supported File Formats Supported File Formats License Requirements Resource Requirements High-Level Design FlowDesign Compiler ProductsSynopsys provides a spectrum of Design Compiler products, whichvary in the complexity of the features offered.

3 Choose the right productfor your Design environment, based on your synthesis the Design Compiler products, you can Produce fast, area-efficient ASIC designs by using user -specifiedgate-array, FPGA, or standard-cell libraries Translate designs from one technology to Compiler user guide Explore Design tradeoffs involving Design constraints such astiming, area, and power under various loading, temperature, andvoltage conditions Synthesize and optimize a finite state machine, includingautomatic state assignment and state minimization Integrate netlist input and netlist or schematic output into third-party environments while still supporting delay information andplace and route constraints Create and partition hierarchical schematics automaticallyThe Design Compiler products include DC Professional DC Expert DC ExpertPlus DC Ultra DC Ultra PlusFigure 1-2 shows the relationship between the features in the DesignCompiler Compiler user GuideFigure 1-2 Design Compiler

4 ProductsThe following sections describe these ProfessionalThe DC Professional tools are applied to typical ASIC designs thatemploy CMOS technology. These designs can utilize multiple clocks;however, the clocks must have the same frequency. DC Professionaldoes not support time borrowing for latch-based set of features provided in the DC Professional product comprisethe core synthesis features. These features are available in all DesignCompiler core synthesis features include Hierarchical compile (top-down or bottom-up) Full and incremental compile techniquesDC UltraDC ExpertPlusDC Ultra PlusDC Compiler user guide Sequential optimization for complex flip-flops and latches I/O pad insertion and optimization Finite state machine (FSM) optimization Buffer balancing (within a hierarchical block)

5 DC ExpertThe DC Expert tools are applied to high-performance ASIC and addition to the core synthesis features, DC Expert provides thefollowing features: Multifrequency clocks Time borrowing for latch-based designs Critical path resynthesis Retiming for minimum clock period In-place optimization Specification of both minimum and maximum constraints foroptimization and timing analysis Synthesis of control logic and certain data-path and structuredlogic Modeling of multiple paths that share a startpoint and endpointbut have different timing Compiler user GuideDC ExpertPlusThe DC ExpertPlustools are applied to high-performance ASIC andIC designs

6 That utilize scan test addition to the DC Expert features, DC ExpertPlus providesintegrated Design -for-test capabilities, including constraint-drivenscan insertion during UltraThe DC Ultra tools are applied to high-performance deep submicronASIC and IC designs, where maximum control over the optimizationprocess is addition to the DC Expert features, DC Ultra provides the followingfeatures: Additional high-effort delay minimization algorithms Support for the cell-degradation Design rule Additional options for theset_cost_priority command Finer optimization control with theset_compile_directivescommand Additional options forreport_timing Support for behavioral optimization of arithmetic (BOA) Support for behavioral retiming (BRT)

7 Compiler user GuideDC Ultra PlusThe DC Ultra Plus tools are applied to high-performance deepsubmicron ASIC and IC designs that utilize scan test addition to the DC Ultra features, DC Ultra Plus provides integrateddesign-for-test InterfacesDesign Compiler provides the following user interfaces:The Design Compiler shell (dc_shell)dc_shell is the command-line interface for the synthesis products( Design Compiler products and options).To run dc_shell, you must have a Design - Compiler book describes the dc_shell AnalyzerThe Design Analyzer interface is the graphical user interface (GUI)for the synthesis products.

8 The GUI includes most synthesiscommands in its menus. You can access any synthesis commandnot implemented in the menus by using the GUI run Design Analyzer, you must have a Design -Analyzer licensein addition to the Design - Compiler Analyzer Reference Manual describes the DesignAnalyzer Compiler user GuideThese user interfaces support both Design Compiler shell language(dcsh) and tool command language (Tcl). For information about theselanguages, see theDesign Compiler Command-Line Interface Compiler OptionsSynopsys provides several products that are integrated into theDesign Compiler environment as options of Design Compiler .

9 Unlessotherwise stated, you must have the Design Compiler product to usethese Compiler ProductsThe HDL Compiler products include HDL Compiler for Verilog VHDL CompilerThese products read and write Verilog or VHDL Design files. The HDLC ompiler product reads these Design files and performs translationand architectural optimization of the designs. For more informationabout the HDL Compiler products, see theHDL Compiler for VerilogReference Manual or theVHDL Compiler Reference Compiler user GuideRTL AnalyzerThe RTL Analyzer product measures Design performance and relatesit directly to HDL source code.

10 It allows you to locate the source codeunderlying timing-, area-, and power-related issues in a Design andto refine the source code before and after synthesis. For moreinformation, see theRTL Analyzer user CompilerThe FPGA Compiler product is available either as a stand-aloneproduct or as an option of Design Compiler . As an option to DesignCompiler, FPGA Compiler enables input of FPGA technology librariesand data formats as well as providing FPGA-specific optimizationalgorithms with features for high-performance FPGA implementations.