Design Compiler User Guide

1 Design Compiler User GuideVersion , March 2019 Design Compiler User Guide , Version Notice and Proprietary Information 2019 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with , INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR and certain Synopsys product names are trademarks of Synopsys, as set forth other product or company names may be trademarks of their respective and Open-Source Software Licensing NoticesIf applicable, Free and Open-Source Software (FOSS) licensing notices are available in the product LinksAny links to third-party websites included in this document are for your convenience only.

2 Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and This Manual .. xxxCustomer Support.. Compiler IntroductionAbout Design Compiler .. 1-2 Design Compiler NXT .. 1-2 Design Compiler Graphical .. 1-3DC Ultra .. 1-4DC Expert .. 1-5 The Design Compiler Family .. 1-5 About DC Explorer.. 1-6 About HDL Compiler .. 1-7 About Library Compiler .. 1-7 About Power Compiler .. 1-8 About DFT Compiler and DFTMAX .. 1-8 About Design Vision .. 1-8 Design Compiler in the Design Flow.. 1-9 High-Level Design Flow Tasks .. 1-10 Design Terminology .. 1-13 Designs .. 1-13 Design Objects .. 1-14 Design .. 1-14 Reference .. 1-14 Instance or Cell.. 1-15 ContentsivDesign Compiler User Compiler User GuideVersion .. 1-15 Pins.. 1-15 Nets .. 1-15 Relationship Between Designs, Instances, and References .. 1-16 Selecting and Using a Compile Strategy .. 1-16 Optimization Basics .. With Design CompilerRunning Design Compiler .

3 2-2 Design Compiler Modes .. 2-2 Wire Load Mode (Default).. 2-3 Topographical Mode .. 2-3 Multimode .. 2-5 UPF Mode.. 2-5 Working With Licenses .. 2-5 License Requirements .. 2-6 Enabling License Queuing .. 2-6 Listing the Licenses in Use .. 2-7 Checking Out Licenses.. 2-7 Checking DesignWare Licenses .. 2-8 Releasing Licenses.. 2-8 The Setup Files .. 2-9 Naming Rules Section of the . File.. 2-10 Starting the Tool in Wire Load Mode .. 2-11 Starting the Tool in Topographical Mode .. 2-12 Design Compiler Startup Tasks .. 2-12 Entering dcnxt_shell or dc_shell Commands.. 2-13 Redirecting the Output of Commands .. 2-14 Interrupting or Terminating Command Processing .. 2-14 Finding Session Information in the Log Files .. 2-15 Command Log Files .. 2-15 Compile Log Files .. 2-15 File Name Log Files .. 2-17 Using Script Files .. 2-17 Getting Help on the Command Line .. 2-18 Saving Designs and Exiting Design Compiler .. 2-18 The Synthesis Flow .. 2-19 Chapter 1: Contents1-vContentsvDesign Compiler User GuideVersion Design Compiler Session Example.

4 2-23 Using Multicore Technology .. 2-25 Enabling Multicore Functionality .. 2-25 Measuring Runtime .. 2-26 Runtime Improvement Techniques Outside of Synthesis .. 2-27 Running Commands in the Background .. 2-27 Verification Guidance Support .. 2-28 Reporting Jobs Submitted To Run in the Background .. 2-28 Enabling Parallel Command Execution .. 2-29 Running Commands in Parallel in the Foreground.. 2-29 Supported Commands for Parallel Execution.. 2-30 Parallel Command Execution Design Flow .. for SynthesisManaging the Design Data .. 3-2 Controlling the Design Data.. 3-2 Organizing the Design Data.. 3-3 Partitioning for Synthesis .. 3-4 Partitioning for Design Reuse .. 3-5 Keeping Related Combinational Logic Together .. 3-5 Registering Block Outputs .. 3-7 Partitioning by Design Goal .. 3-7 Partitioning by Compile Technique .. 3-8 Keeping Sharable Resources Together .. 3-8 Keeping User-Defined Resources With the Logic They Drive .. 3-9 Isolating Special Functions.

5 3-10 HDL Coding for Synthesis.. 3-11 Writing Technology-Independent HDL .. 3-11 Inferring Components .. 3-12 Using HDL Constructs .. 3-14 General HDL Constructs.. 3-14 Using Verilog Macro Definitions .. 3-18 Using VHDL Port Definitions.. 3-18 Writing Effective Code .. 3-19 Guidelines for Identifiers .. 3-19 Guidelines for Expressions .. 3-20 ContentsviDesign Compiler User Compiler User GuideVersion for Functions .. 3-21 Guidelines for Modules .. 3-22 Instantiating RTL PG Pins .. 3-22 Performing Design Exploration .. 3-23 Creating Constraints .. Up and Working With LibrariesSelecting a Semiconductor Vendor.. 4-3 Library Requirements .. 4-3 Logic Libraries .. 4-4 Target Libraries .. 4-5 Link Libraries .. 4-6 Symbol Libraries .. 4-6 DesignWare Libraries .. 4-7 Physical Libraries.. 4-7 Specifying Logic Libraries .. 4-9 Specifying DesignWare Libraries.. 4-10 Specifying a Library Search Path .. 4-10 Setting Minimum Timing Libraries .. 4-11 Specifying Physical Libraries.

6 4-11 Using TLUPlus Files for RC Estimation .. 4-12 Working With Libraries .. 4-13 Loading Libraries .. 4-14 Listing Libraries .. 4-14 Reporting Library Contents .. 4-14 Specifying Library Objects .. 4-15 Excluding Cells From the Target Libraries .. 4-15 Verifying Library Consistency .. 4-16 Removing Libraries From Memory .. 4-16 Saving Libraries .. 4-17 Target Library Subsets .. 4-17 Specifying Target Library Subsets .. 4-17 Setting Target Library Subset Examples.. 4-19 Checking Target Library Subsets .. 4-20 Chapter 1: Contents1-viiContentsviiDesign Compiler User GuideVersion Target Library Subsets .. 4-20 Removing Target Library Subsets .. 4-20 Library Subsets for Sequential Cells and Instantiated Combinational Cells .. 4-20 Specifying the Library Cell Subsets .. 4-21 Reporting the Library Cell Subsets .. 4-22 Removing the Library Cell Subsets .. 4-23 Link Library Subsets .. 4-23 Specifying Link Library Subsets.. 4-23 Setting Link Library Subset Examples.

7 4-25 Reporting Link Library Subsets .. 4-25 Removing Link Library Subsets .. 4-25 Library-Aware Mapping and Synthesis .. 4-26 Generating the ALIB File .. 4-26 Using the ALIB Library .. 4-26 Analyzing Multithreshold Voltage Library Cells .. 4-27 Handling Black Boxes .. 4-29 Supported Black Boxes .. 4-29 Black Box Flow .. 4-30 Defining Timing in Quick Timing Model Format .. 4-31 Defining Physical Dimensions .. 4-32 Estimating the Size of Black Boxes .. 4-32 Determining the Gate Equivalent Area .. 4-33 Identifying Black Box Cells .. 4-33 Automatic Creation of Physical Library Cells .. a Milkyway DatabaseAbout the Milkyway Database .. 5-2 Required License and Files .. 5-2 Invoking the Milkyway Environment Tool .. 5-3 Guidelines for Using the Milkyway Database .. 5-3 Preparing to Use the Milkyway Database .. 5-4 Writing the Milkyway Database.. 5-5 Important Points About the write_milkyway Command .. 5-5 Limitations When Writing Milkyway Format .. 5-6 ContentsviiiDesign Compiler User Compiler User GuideVersion With Designs in MemoryReading Designs.

8 6-3 Supported Design Input Formats .. 6-3 Reading HDL Files.. 6-3 Reading Designs With Dependencies Automatically .. 6-4 Running the read_file Command .. 6-5 Running the analyze and elaborate Commands.. 6-5 Differences Between the read_file Command and the analyze andelaborate Commands .. 6-6 Running the read_verilog or read_vhdl Command .. 6-7 Reading .ddc Files .. 6-7 Reading .db Files .. 6-8 Listing Designs in Memory .. 6-8 Setting the Current Design .. 6-9 Linking Designs .. 6-9 How the Tool Resolves References .. 6-10 Locating Designs by Using a Search Path .. 6-11 Changing Design References .. 6-12 Querying Design References.. 6-13 Mapping Physical Variant Cells in Netlists or DEF Files .. 6-13 Listing Design Objects .. 6-14 Specifying Design Objects .. 6-15 Using a Relative Path .. 6-15 Using an Absolute Path .. 6-16 Using Attributes .. 6-17 Setting Attribute Values.. 6-18 Viewing Attribute Values .. 6-19 Saving Attribute Values.. 6-20 Defining Attributes.

9 6-20 Propagating Attributes .. 6-21 Removing Attributes .. 6-22 The Object Search Order .. 6-22 Creating Designs .. 6-23 Copying Designs.. 6-23 Renaming Designs .. 6-24 Chapter 1: Contents1-ixContentsixDesign Compiler User GuideVersion the Design Hierarchy .. 6-25 Adding Levels of Hierarchy .. 6-26 Removing Levels of Hierarchy .. 6-27 Ungrouping Hierarchies Before Optimization .. 6-27 Ungrouping Hierarchies Explicitly During Optimization .. 6-28 Ungrouping Hierarchies Automatically During Optimization .. 6-29 Preserving Hierarchical Pin Timing Constraints During Ungrouping .. 6-30 Merging Cells From Different Subdesigns .. 6-31 Editing Designs .. 6-31 Translating Designs From One Technology to Another .. 6-33 Translating Designs in Design Compiler Wire Load Mode .. 6-34 Translating Designs in Design Compiler Topographical Mode .. 6-34 Restrictions on Translating Between Technologies .. 6-35 Removing Designs From Memory .. 6-35 Saving Designs .. 6-36 Supported Design File Output Formats.

10 6-36 Writing a Design Netlist or Schematic .. 6-37 Writing To a Milkyway Database .. 6-37 Saving Designs Using GUI Commands .. 6-37 Ensuring Name Consistency Between the Design Database and the Netlist .. 6-38 Specifying the Name Mapping and Replacement Rules .. 6-38 Resolving Naming Problems in the Flow .. 6-38 Avoiding Bit-Blasted Ports in SystemVerilog and VHDL Structures .. 6-39 Summary of Commands for Changing Names .. the Design EnvironmentOperating Conditions .. 7-3 Defining Operating Conditions .. 7-3 Reporting Operating Conditions .. 7-4 Modeling the System Interface .. 7-4 Defining Drive Characteristics for Input Ports .. 7-5 Defining Loads on Input and Output Ports.. 7-7 Defining Fanout Loads on Output Ports .. 7-7 Setting Logic Constraints on Ports .. 7-8 ContentsxDesign Compiler User Compiler User GuideVersion Assignment of Any Signal to an Input .. 7-9 Specifying Input Ports as Always One or Zero .. 7-10 Wire Load Models .. 7-10 Hierarchical Wire Load Models.