DS125DF111 Multi-Protocol 2-Channel 9.8 - 12.5 …

1 VDDOUTA_POUTA_NINB_PINB_NSCLADDR0/LOCKSD AINA_PINA_NOUTB_POUTB_N100nF100nF25 F(2x)REFCLK_INEN_SMBGND1k:1k:1k:1k:2k:2k :ADDR1/VODB/DONE# :22nFLPF_REF_ALPF_CP_A22nFLPF_REF_BLPF_C P_BDAPVIN1 &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityDS125DF111 SNLS450A JANUARY2014 - Gb/s Retimer1 Features3 DescriptionTheDS125DF111is a dualchannel(1-lane1 Pin CompatibleRetimerFamilybidirectional)ret imerwithintegratedsignal DS110DF111with - input DS125DF111with - (CTLE),clockanddatarecovery(CDR)andtrans mitdriveron each AdaptiveCTLE:33 dB Max Boostat Self Tuning5-TapDFEThe DS125DF111with its on-chipDecisionFeedback RawEqualizedand RetimedDataLoopbackEqualizer(DFE)canenha ncethereachand AdjustableTransmitVOD: 600 to 1300mVp-probustnessof long,lossy,cross-talk-impairedhigh SettableTx De-EmphasisDriver0 to 12dBspeedseriallinksto achieveBER< 1x10 15.

2 For lessdemandingapplications/interconnects, the DFEcan Low PowerConsumption:220 mW/Channelbe switchedoff andachievethesameBER Locksto Half/ pin-compatible. On-ChipEye Monitor(EOM),PRBSG eneratorEachchannelof the DS125DF111independently InputSignalDetection,CDRL ocklocksto specificserialdataat to any supportedsub-rateof thesedata SMBus,EEPROM,or Pin BasedConfiguration 4-mmx 4-mm,24-PinWQFNP ackageProgrammabletransmitde-emphasisdri veroffersprecisesettingsto meetthe SFF-8431outputeye OperatingTempRange: 40 C to 85 (CTLEandDFE)enableslongerdistance2 Applicationstransmissionin lossycopperinterconnectand FrontPort idealfor use in frontport paralleloptical SFF-8431moduleapplicationsto resetthe jitterbudgetand 10G/1 GEthernetretimehigh speedserialdata. CPRID eviceInformation(1)PARTNUMBERPACKAGEBODY SIZE(NOM) DS125DF111 WQFN(24) mm mm(1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand JANUARY2014 Applicationand Pin Deviceand Mechanical,Packaging,and RevisionHistoryNOTE.

3 Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (January2014)to RevisionAPage AddedPin Configurationand Functionssection,HandlingRatingtable,Fea tureDescriptionsection,DeviceFunctionalM odes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and 2014 2015,TexasInstrumentsIncorporatedProduct FolderLinks: DS125DF111 OUTA+OUTA-OUTB+ADDR0/LOCKVIN18 INB+INB-17141316 LOS/INT#LPF_CP_BLPF_REF_BREFCLK_ININA+IN A-OUTB-15 VDD242322212019111281097 LPF_CP_AENSMB12563 SCL/DEMBLPF_REF_ASDA/DEMA4 VDDTX_DIS/LPBKVODA/READEN#ADDR1/VODB/DON E#TOP VIEWDAP = GND4mm x 4mm, JANUARY2014 REVISEDJUNE20155 Pin ConfigurationAndFunctionsRTWP ackage24-PinWQFNTop ViewPin FunctionsPINI/O 7, 8O, CMLI nvertingand couplingOUTB 20, 19O, CMLI nvertingand couplingINA 24, 23I, CMLI nvertingand on-chip 100 terminatingresistorconnectsINA+to INA-InputsrequireAC recommends100 nF SFP+applications,AC couplingis includedas part of the SFP+ 11, 12I, CMLI nvertingand on-chip 100 terminatingresistorconnectsINB+to INB-InputsrequireAC recommends100 nF SFP+applications,AC couplingis includedas part of the SFP+ ,LPF_REF_A2, 1I/O.

4 AnalogLoopfilter connection,placea 22 nF 10%capacitorin seriesbetweenLPF_CP_Aand LPF_REF_ALPF_CP_B,LPF_REF_B17, 18I/O, analogLoopfilter connection,placea 22 nF 10%capacitorin seriesbetweenLPF_CP_Band LPF_REF_BREFERENCECLOCKI/OREFCLK_IN14I, LVCMOS25 MHz 100 ppmclockfromexternalOscillatorCopyright 2014 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks:DS125DF111DS125DF111 SNLS450A JANUARY2014 Functions(continued)PINI/O , LVCMOSLOCKVOHis referencedto this pin is sharedwith strapinputfunctionsreadat Addressvalueloadedintopin 16 (ADDR0)at startupchangesthe definitionof the LOCKpin the SharedRegisterDefinitionin Table7 for #13O, OpenDrainOutputis drivenLOWwhena validsignalis presenton INA is lost (LOS).This outputcan be redefinedas an INT#signalwhichwill be drivenLOWfor any of the followingconditions.

5 (1)1. The EOMcheckreturnsa valuebelowthe , 4-LevelSystemManagementBus (SMBus)enablepinHIGH= RegisterAccess,SMBusSlavemodeFLOAT= SMBusMasterreadfromExternalEEPROM20 K to GND= ReservedLOW= ExternalPin sectiononPin ModeLimitationSDA4I, SMBusDataInput/ OpenDrainOutputO, OpenDrainExternalpull-upresistoris is V LVCMOS tolerant(1)SCL5I, SMBusClockinputin also be an opendrainoutputinO, OpenDrainSMBusmastermodePin is V LVCMOST olerant(1)TX_DIS6I, 4-LevelDisablethe OUTB transmitterHIGH= OUTAE nabled/OUTBD isabledFLOAT= Reserved20 K to GND= ReservedLOW= OUTA/OUTBE nabled(normaloperation)ADDR016I, LVCMOSThis pin sets the SMBusaddressfor the pin is a stateis readon power-upto set the SMBusaddressin latchedvalueof ADDR0readatstartupwill changethe the SharedRegisterDefinitionin Table7 for moredetails.

6 (2)ADDR1/DONE#10IO, LVCMOSThis pin sets the SMBusaddressfor the retimerin #.VOHis referencedto #goeslow toindicatethat the SMBusmasterEEPROM readhas beencompletedinSMBusMasterMode(2)READEN# 9I, a singleEEPROM,the READEN#inputcan be daisychainedto the DONE# SMBusSlaveModethis pin shouldbetied to Logic0.(3)PIN CONTROL(ENSMB= LOW)(4)DEMA4I, 4-LevelSet CHAoutputde-emphasislevelin pin controlmode(3)DEMB5I, 4-LevelSet CHBoutputde-emphasislevelin pin controlmode(3)LPBK6I, 4-LevelHIGH= INA goesto OUTA,INB goesto OUTBFLOAT= INB goesto OUTAand OUTB20 K to GND= INA goesto OUTAand OUTBLOW= INA goesto OUTB,INB goesto OUTA(3)VODA9I, 4-LevelSet CHAoutputlaunchamplitudein pin controlmode(3).VODB10I, 4-LevelSet CHBoutputlaunchamplitudein pin controlmode(3)(1)The LOS/INT#pin is an opendrainoutputwhichrequiresexternalpull -upresistor(typicallyconnectedto V or V for systemlogiccompatibility)to achievea HIGH level.

7 (2)This pin is sharedwith otherfunctions.(3)This pin is sharedwith otherfunctions.(4)Whenin pin controlmode,the DS125DF111deviceoperatesat , , , , , , ,or has limitedVODand 2014 2015, JANUARY2014 REVISEDJUNE2015 Pin Functions(continued)PINI/O , 22 PowerVDD= V 5%. See :VDD= V is suppliedthe requirede-couplingcaps;no externalsupplyis :VDDinput= V 5%.VIN15 PowerRegulatorInput(3)with :VINinput= V 10%. :VINS upplyInput= V 5%. Connectdirectlyto exposedpad at the centerof the packagemustbe connectedtogroundplaneof the boardwith at least4 vias to lowerthe groundimpedanceand improvethe thermalperformanceof the packageCopyright 2014 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks:DS125DF111DS125DF111 SNLS450A JANUARY2014 (unlessotherwisenoted)(1)(2)MINMAXUNITS upplyVoltage(VDD) (VIN) ( ) ( ) + 3030mAStoragetemperature,Tstg 40125 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

8 (2)Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay solderingspecifications,seeproductfolder at (HBM),per ANSI/ESDA/JEDECJS-001,all 3000pins(1)V(ESD)ElectrostaticdischargeV Chargeddevicemodel(CDM),per JEDEC specificationJESD22- 1500C101,all pins(2)(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.(2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (1) V V 4025+85 CSMBus(SDA,SCL) (1)Typicalvaluesrepresentthe mostlikelyparametricnormas determinedat the time of designand vary overtime and will also dependon the applicationand (1)RTW(WQFN)UNIT24 PINSR JAJunction-to-ambientthermalresistance35 C/WR JC(top)Junction-to-case(top)thermalresis tance34 C/WR C/W C/W C/WR JC(bot)Junction-to-case(bottom) C/W(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport, 2014 2015, JANUARY2014 (1)MAXUNITR_BaudInputbaudrate (primaryVCOrange)

9 Full 2 Half 4 8 100 ppm25 MHzDCREFCLKR eferenceClockDutyCycle40%50%60%POWERSUPP LYCURRENTA verageSupplyCurrent,DefaultSettings,CHAa nd CHBL ocked175mADFEE nabledAverageSupplyCurrent,CHAandCHBL ockedDS125DF111 CurrentConsumption155mAIDDD efaultSettingsexceptDFE(WholeDevice)Disa bledMaximumTransientSupplyCurrentDefault Settings:CHAand CHB294333mAvalidinputsignaldetectedCHAan d CHBacquiringLOCK(2)50 Hz to 100 Hz100mVp-pNTpsSupplyNoiseTolerance100 Hz to 10 MHz40mVp-p10 MHzto GHz10mVp-pLVCMOS(ADDR[1:0],READEN#,REFCL K_IN,DONE#,LOCK) V or V V or V -3 mA2 VINVOH2 HighleveloutputvoltageIOH= 100 AVIN- leveloutputvoltageIOL= 3 GNDor VIN 1515 A4-LEVELINPUTS(ENSMB,DEMA,DEMB,LPBK,TX_D IS,VODA,VODB)IIH-RInputleakagecurrentHig hVINPUT= VIN80 AIIL-RInputleakagecurrentLowVINPUT= GND 160 AOPENDRAIN(LOS/INT#)VOLLow leveloutputvoltageIOL= 3 :Defaultlevelto assertSDH18mVp-pON ThresholdLevelSignalDetect, ,PRBS31 SignalDetect.

10 Defaultlevelto de-assertSDL14mVp-pOFFT hresholdLevelSignalDetect, ,PRBS31 CMLRX INPUTSR_RdDC InputdifferentialResistance80100120 SDD1110 MHz GHz - Launchamplitudeof driverSourceTransmitSignalLevel1600mVp-p LAUNCH connectedto DS125DF111inputs(3)(1)Typicalvaluesrepre sentthe mostlikelyparametricnormas determinedat the time of designand vary overtime and will also dependon the applicationand configuration.(2)Peakcurrentonly occursduringlock acquisition,limit is for powersupplydesignnot neededfor thermalcalculations.(3)DS125DF111equaliz eris optimizedto adaptto Tx Launchamplitudesbetween600 - 1200mV. Amplitudesaboveor belowthis rangewill reducethe 2014 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback7 ProductFolderLinks:DS125DF111DS125DF111 SNLS450A JANUARY2014 (continued)PARAMETERTESTCONDITIONSMINTYP (1)MAXUNITTRANSMITJITTERSPECS(4)TTJT otalJitter(@ BER= 1E-12)PRBS7, , (RMS)TDJD eterministicJitterPRBS7, , UI SjBWP LLPLL Bandwidth-3 tolerance> Dj, Pj, and (Register0x31[6:5])CTLESet - no AutoadaptDisableHEO/VEOLockMonitor-(Regi ster0x3E[7])HEO/VEOthresholdsset to 0 -(Register0x6A[7:0]) Table9 CDRR esetand Release- (Register0x0A[3:2])SignalDetectPresetand Release-Beforeinputsignalis present(Register0x14[7.)]