DS90UB949-Q1 1080p HDMI to FPD-Link III Bridge Serializer ...

1 Product Sample & Technical Tools & Support &. Folder Buy Documents Software Community DS90UB949-Q1 . SNLS452 NOVEMBER 2014. DS90UB949-Q1 1080p HDMI to FPD-Link III Bridge Serializer 1 Features 3 Description 1 Supports TMDS Clock up to 170 MHz for WUXGA The DS90UB949-Q1 is a HDMI to FPD-Link III Bridge (1920x1200) and 1080p60 Resolutions with 24-Bit device which, in conjunction with the FPD-Link III. DS90UB940-Q1/DS90UB948-Q1 deserializers, Color Depth provides 1-lane or 2-lane high-speed serial streams Single and Dual FPD-Link III Outputs over cost-effective 50 single-ended coaxial or 100 . High-Definition Multimedia (HDMI) Inputs differential shielded twisted-pair (STP) cables.

2 It HDMI-Mode DisplayPort (DP++) Inputs serializes a HDMI input supporting video resolutions up to WUXGA and 1080p60 with 24-bit HDMI Audio Extraction for up to 8 Channels color depth. High Speed Back Channel Supporting GPIO up to The FPD-Link III interface supports video and audio 2 Mbps data transmission and full duplex control, including Supports up to 15 Meters of Cable with Automatic I2C and SPI communication, over the same Temperature and Aging Compensation differential link. Consolidation of video data and Tracks Spread Spectrum Input Clock to Reduce control over two differential pairs reduces the EMI interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage I2C (Master/Slave) with 1 Mbps Fast-Mode Plus differential signaling, data scrambling, and SPI Pass-Through Interface randomization.

3 In backward compatible mode, the Backward compatible with DS90UB926Q-Q1 and device supports up to WXGA and 720p resolutions DS90UB928Q-Q1 FPD-Link III Deserializers with 24-bit color depth over a single differential link. Automotive Grade Product: AEC-Q100 Grade 2 The DS90UB949-Q1 supports multi-channel audio Qualified received through HDMI or an external I2S interface. The device also supports an optional auxiliary audio 2 Applications interface. Automotive Infotainment: Device Information(1). IVI Head Units and HMI Modules PART NUMBER PACKAGE BODY SIZE (NOM). Rear Seat Entertainment Systems DS90UB949-Q1 VQFN RGC (64) mm X mm Digital Instrument Clusters (1) For all available packages, see the orderable addendum at Security and Surveillance Camera the end of the datasheet.

4 Consumer Input HDMI Port 4 Applications Diagram VDDIO VDDIO. ( / ). FPD-Link HDMI FPD-Link III (Open LDI). 2 Lane CLK+/- IN_CLK-/+. DOUT0+ RIN0+ D0+/- IN_D0-/+ RIN0- DOUT0- D1+/- IN_D1-/+. Graphics DOUT1+ RIN1+ D2+/- LVDS. Processor Display IN_D2-/+ DOUT1- RIN1- D3+/- 1080p60. DS90UB949-Q1 DS90UB948-Q1 or Graphic CEC. Serializer Deserializer CLK2+/- Processor DDC. HPD D4+/- D5+/- I2C. I2C IDx D6+/- IDx D_GPIO D7+/- D_GPIO. (SPI) (SPI). HDMI High Definition Multimedia Interface 1. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

5 DS90UB949-Q1 . SNLS452 NOVEMBER 2014 Table of Contents 1 Features .. 1 Feature 18. 2 Applications .. 1 Device Functional 31. 3 Description .. 1 33. Register Maps .. 37. 4 Applications Diagram .. 1. 5 Revision 2 9 Application and Implementation .. 66. Applications 66. 6 Pin Configuration and Functions .. 3. Typical Applications .. 66. 7 7. 10 Power Supply Recommendations .. 71. Absolute Maximum Ratings .. 7. Power Up Requirements And PDB 71. Handling 7. Recommended Operating 7 11 72. Layout Guidelines .. 72. Thermal Information .. 8. Layout Example .. 73. DC Electrical Characteristics .. 9. AC Electrical 11 12 Device and Documentation Support .. 74. DC And AC Serial Control Bus Characteristics.

6 12 Documentation Support .. 74. Recommended Timing for the Serial Control Bus .. 13 Trademarks .. 74. Typical Characteristics .. 16 Electrostatic Discharge Caution .. 74. Glossary .. 74. 8 Detailed Description .. 17. Overview .. 17 13 Mechanical, Packaging and Orderable Functional Block Diagram .. 17. Information .. 74. 5 Revision History DATE REVISION NOTES. November 2014 * Initial release. 2 Submit Documentation Feedback Copyright 2014, Texas Instruments Incorporated Product Folder Links: DS90UB949-Q1 . DS90UB949-Q1 . SNLS452 NOVEMBER 2014. 6 Pin Configuration and Functions 64 PINS. Top View I2S_CLK / GPIO8_REG. I2S_WC / GPIO7_REG. I2S_DB / GPIO5_REG. I2S_DA / GPIO6_REG.

7 I2S_DD / GPIO3. I2S_DC / GPIO2. REM_INTB. DDC_SDA. DDC_SCL. VDDL11. RX_5V. VDDIO. HPD. NC1. NC0. X1. 48. 47. 46. 45. 44. 43. 42. 41. 40. 39. 38. 37. 36. 35. 34. 33. IN_CLK- 49 32 MODE_SEL1. IN_CLK+ 50 31 PDB. VDD18 51 30 RES2. VDDHA11 52 29 RES1. NC2 53 28 VDDHS11. VDDHA11 54 27 DOUT0+. IN_D0- 55 DS90UB949-Q1 26 DOUT0- IN_D0+ 56 25 VDDS11. 64 VQFN. VTERM 57 24 VDD18. Top View VDDHA11 58 23 DOUT1+. IN_D1- 59 22 DOUT1- IN_D1+ 60 21 VDDHS11. VDDHA11 61 DAP = GND 20 LFT. IN_D2- 62 19 IDx IN_D2+ 63 18 MODE_SEL0. VDD18 64 17 VDDP11. 10. 11. 12. 13. 14. 15. 16. 1. 2. 3. 4. 5. 6. 7. 8. 9. D_GPIO0 / MOSI. VDDA11. CEC. RES0. VDDIO. SDIN / GPIO0. SWC / GPIO1. SCLK / I2 CSEL. VDDL11.

8 D_GPIO1 / MISO. D_GPIO2 / SPLK. D_GPIO3 / SS. INTB. SDA. SCL. MCLK. Pin Functions PIN. I/O, TYPE DESCRIPTION. NAME NO. HDMI TMDS INPUT. IN_CLK- 49 I, TMDS TMDS Clock Differential Input IN_CLK+ 50. IN_D0- 55 I, TMDS TMDS Data Channel 0 Differential Input IN_D0+ 56. IN_D1- 59 I, TMDS TMDS Data Channel 1 Differential Input IN_D1+ 60. IN_D2- 62 I, TMDS TMDS Data Channel 2 Differential Input IN_D2+ 63. OTHER HDMI. HPD 42 O, Open- Hot Plug Detect Output. Pull up to RX_5V with a 1k resistor Drain RX_5V 43 I HDMI 5V Detect Input DDC_SDA 44 IO, Open- DDC Slave Serial Data Drain Pull up to RX_5V with a 47k resistor DDC_SCL 45 I, Open-Drain DDC Slave Serial Clock Pull up to RX_5V with a 47k resistor Copyright 2014, Texas Instruments Incorporated Submit Documentation Feedback 3.

9 Product Folder Links: DS90UB949-Q1 . DS90UB949-Q1 . SNLS452 NOVEMBER 2014 Pin Functions (continued). PIN. I/O, TYPE DESCRIPTION. NAME NO. CEC 1 IO, Open- Consumer Electronic Control Channel Input/Output Interface. Drain Pull-up with a 27k resistor to X1 39 I, LVCMOS Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be connected to a 25 MHz (1000ppm), 45-55% duty cycle clock source at CMOS-level Leave it open if unused. FPD-Link III SERIAL. DOUT0- 26 O FPD-Link III Inverting Output 0. The output must be AC-coupled with a F capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers DOUT0+ 27 O FPD-Link III True Output 0.

10 The output must be AC-coupled with a F capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers DOUT1- 22 O FPD-Link III Inverting Output 1. The output must be AC-coupled with a F capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers DOUT1+ 23 O FPD-Link III True Output 1. The output must be AC-coupled with a F capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers LFT 20 Analog FPD-Link III Loop Filter Connect to a 10nF capacitor to GND. CONTROL. SDA 14 IO, Open- I2C Data Input / Output Interface Drain Open drain. Must have an external pull-up to resistor to or See I2 CSEL pin.