Electrical Compliance Test Specification …

1 superspeed Electrical Compliance i Electrical Compliance Test Specification superspeed Universal Serial Bus Date: March 10, 2015 Revision: ii superspeed Electrical Compliance Copyright 2015, USB Implementers Forum, Inc. All rights reserved. A LICENSE IS HEREBY GRANTED TO REPRODUCE THIS Specification FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, IS GRANTED OR INTENDED HEREBY. USB-IF AND THE AUTHORS OF THIS Specification EXPRESSLY DISCLAIM ALL LIABILITY FOR INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS Specification . USB-IF AND THE AUTHORS OF THIS Specification ALSO DO NOT WARRANT OR REPRESENT THAT SUCH IMPLEMENTATION(S) WILL NOT INFRINGE THE INTELLECTUAL PROPERTY RIGHTS OF OTHERS. THIS Specification IS PROVIDED "AS IS" AND WITH NO WARRANTIES, EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE. ALL WARRANTIES ARE EXPRESSLY DISCLAIMED. NO WARRANTY OF MERCHANTABILITY, NO WARRANTY OF NON-INFRINGEMENT, NO WARRANTY OF FITNESS FOR ANY PARTICULAR PURPOSE, AND NO WARRANTY ARISING OUT OF ANY PROPOSAL, Specification , OR SAMPLE.

2 IN NO EVENT WILL USB-IF OR USB-IF MEMBERS BE LIABLE TO ANOTHER FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA OR ANY INCIDENTAL, CONSEQUENTIAL, INDIRECT, OR SPECIAL DAMAGES, WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THE USE OF THIS Specification , WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. Scope of this Revision This revision of the Specification describes the testing to be applied to hardware based on the Universal Serial Bus Specification , revision iv superspeed Electrical Compliance This document is an intermediate draft for comment only and is subject to change without notice. *Third-party brands and names are the property of their respective owners. Significant Contributors: Dan Froelich (author) Intel Steven Sanders Teledyne Lecroy Howard Heck (author) Intel Dan Weinlader Synopsys Jim Choate Agilent Hajime Nozaki NEC Mike Engbretson Tektronix Jin-sheng Wang Texas instruments Christopher Skach Tektronix Masami Katagiri NEC Greg Daly Intel Dan Smith Seagate David Li Teledyne-Lecroy Randy White Tektronix John Stonick Synopsys Jim Mueller Teledyne Lecroy Table of Contents REVISION HISTORY.

3 IV TABLE OF CONTENTS .. V 1 INTRODUCTION .. 2 Related Documents .. 2 USB Compliance .. 2 2 TEST DESCRIPTIONS .. 2 Low Frequency Periodic Signaling TX Test.. 2 Low Frequency Periodic Signaling RX Test.. 2 Transmitted Eye Test .. 3 Transmitted SSC Profile Test .. 4 Receiver Jitter Tolerance Test .. 5 Chapter 1: superspeed Electrical Compliance 1 Chapter 1: Introduction superspeed Electrical Compliance 2 1 Introduction This document provides the Compliance criteria and test descriptions for superspeed USB devices, hubs and host controllers that conform to the Universal Serial Bus Specification , rev It is relevant for anyone building superspeed USB hardware. These criteria address the Electrical requirements for a superspeed physical layer design. Test descriptions provide a high level overview of the tests that are performed to check the Compliance criteria. The descriptions are provided with enough detail so that a reader can understand what the test does.

4 The descriptions do not describe the actual step-by-step procedure to perform the test. Related Documents [1] Universal Serial Bus Specification , revision , November 12, 2008 [2] USB Super Speed Electrical Compliance Methodology, revision [3] Universal Serial Bus Specification , Revision , April 27, 2000. [4] USB-IF USB Electrical Test Specification , Version , January 2005. USB Compliance USB 2,0 testing is required for USB devices and is covered by a separate Compliance testing program. Refer to [3] and [4] for details. 2 Test Descriptions Low Frequency Periodic Signaling TX Test. This test verifies that the low frequency periodic signal transmitter meets the timing requirements when measured at the Compliance test port. Overview of Test Steps 1. The test performs the following steps. Connect the DUT to a simple breakout test fixture. Disconnect bus power if the DUT is a bus powered device. 2. Power on the device under test (connect bus powered if DUT is a bus powered device) and let it pass through the state to the substate.

5 3. Trigger on the initial LFPS burst sent by the DUT and capture the first five bursts for 4. Measure the following LFPS parameters and compare against the USB Specification requirements: tburst, trepeat, tperiod, tRiseFall2080, Duty cycle, VCM-AC-LFPS, and VTX-DIFF-PP-LFPS. For these measurements the start of an LFPS burst is defined as starting when the absolute value of the differential voltage has exceeded 100 mV and the end of an LFPS burst is defined as when the absolute value of the differential voltage has been below 100 mV for 50 ns. tperiod, tRiseFall2080, Duty cycle, VCM-AC-LFPS, and VTX-DIFF-PP-LFPS are only measured during the period from 100 nanoseconds after the burst start to 100 nanoseconds before the burst stop. Low Frequency Periodic Signaling RX Test. This test verifies that the DUT low frequency periodic signal receiver recognizes LFPS signaling with voltage swings and duty cycles that are at the limits of what the Specification allows. The link test Specification includes test that vary additional LFPS parameters to test the LFPS receiver.

6 Overview of Test Steps The test performs the following steps. Chapter 2: Test Descriptions superspeed Electrical Compliance 3 1. Connect the DUT to a simple breakout test fixture. Disconnect bus power if the DUT is a bus powered device. 2. Power on the device under test (connect bus powered if DUT is a bus powered device) and let it pass through the state to the substate. 3. Trigger on the initial LFPS burst sent by the DUT and send LFPS signals to the DUT with the following parameters: a. tPeriod 50 ns. b. VTX-DIFF-PP-LFPS 800 mV. c. Duty Cycle 50% 4. The test passes if the device recognizes the LFPS and starts sending the TSEQ sequence. 5. The test is repeated with the following parameters: a. tPeriod 50 ns, VTX-DIFF-PP-LFPS 1200 mV, Duty Cycle 50%. b. tPeriod 50 ns, VTX-DIFF-PP-LFPS 1000 mV, Duty Cycle 40%. c. tPeriod 50 ns, VTX-DIFF-PP-LFPS 1000 mV, Duty Cycle 60%. Transmitted Eye Test This test verifies that the transmitter meets the eye width, deterministic jitter and random jitter requirements when measured at the Compliance test port with nominal transmitter equalization and after processing with the appropriate channels and post processing as shown in Table 2-1.

7 Connector Type Channel Reference Equalizer Std-A 3m Cable + 5 PCB Long Channel Std-B 3m Cable + 11 PCB Long Channel Micro-B 1m Cable + 11 PCB Long Channel Micro-AB (Host Only) 1m Cable + 5 PCB + Micro-A to Std-A Receptacle adapter Long Channel Micro-AB (DRD) 1m Cable + 11 PCB (device mode) 1m Cable + 5 PCB + Micro-A to Std-A Receptacle adapter (host mode) Both tests are required Long Channel Tethered (Standard A Plug) 11 PCB Long Channel All Types No Channel (fixture only) Short Channel Table 2-1 Channels and Reference Equalizer for Testing Device Types Note: Refer to for s-parameter files for embedding the long channels when using breakout fixtures. In order to comprehend noise effects, such as crosstalk, it is up to the DUT manufacturer to make sure that any other links are active for the various DUT types. Chapter 2: Test Descriptions superspeed Electrical Compliance 4 Overview of Test Steps The test runs in the substate, and performs the following steps.

8 1. Connect the DUT to a simple break-out test fixture without VBUS supplied. 2. Power on the device under test and apply VBUS if the DUT is not a host, let it pass through the state to the Compliance state. SSC shall be enabled. 3. Transmit the CP0 Compliance pattern on the superspeed USB port under test and capture the transmitted waveform on a high speed oscilloscope over a minimum of 1,000,000 unit intervals (200 sec) at a sample rate of no more than 25 ps in a single scope capture. 4. Send a to the RX port of the device under test to cause the Compliance pattern to transition to CP1. A single burst is sent with the following parameters: a. 100 nanosecond duration. b. 20 Mhz frequency (2 periods). 5. Transmit the CP1 Compliance pattern on the superspeed USB port under test and capture the transmitted waveform on a high speed oscilloscope over a minimum of 1,000,000 unit intervals (200 sec) at a sample rate of no more than 25 ps in a single scope capture. 6. The required Compliance channel shown in Table 2-1 for the connector type under test is embedded to the measured CP0 and CP1 data.

9 The following analysis in steps 7-9 is done applying the appropriate equalizer shown in Table 2-1 and JTF in the waveform analysis. 7. Compute the data eye using CP0 and compare it against the normative transmitter specifications contained in table 6-12 of the USB Specification . 8. Compute Rj using the CP1 data and compare it against the normative transmitter specifications contained in table 6-12 of the USB Specification . 9. Compute the total jitter at 10-12 BER using the CP0 data to compute a measured Tj and the Rj value from CP1 with the dual dirac method and compare it against the normative transmitter Specification contained in table 6-12 of the USB Specification . Note: Extrapolate Tj E-12 based on Tj measured with CP0 and CP1 Rj only. 10. Repeat the analysis in steps 7-9 for the short channel and reference equalizer shown in Table 2-1. Transmitted SSC Profile Test This test verifies that the transmitter meets SSC profile requirements when measured at the Compliance test port with of transmitter equalization and after processing with the JTF.

10 In order to comprehend noise effects, such as crosstalk, it is up to the DUT manufacturer to make sure that any other links are active for the various DUT types. Note: A PCI Express host adaptor is tested in a system that provides a 100 Mhz PCI Express reference clock with a valid SSC profile and in a system with a 100 Mhz PCI Express reference clock that does not have SSC. The host adaptor must pass all tests in both cases. No transmitter testing is done with multiple downstream ports active on hosts/hubs. Overview of Test Steps The test runs in the substate, and performs the following steps. Chapter 2: Test Descriptions superspeed Electrical Compliance 5 1. Connect the DUT to a simple break-out test fixture. 2. Power on the device under test, let it pass through the state to the substate. 3. Send a to the RX port of the device under test to cause the Compliance pattern to transition to CP1. 4. Transmit the CP1 Compliance pattern on the superspeed USB port under test and capture the transmitted waveform on a high speed oscilloscope over a minimum of 1,000,000 unit intervals (200 sec) at a sample rate of no more than 25 ps in a single scope capture.