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1 international technology roadmap FOR semiconductors 2011 EDITION EMERGING RESEARCH DEVICES THE ITRS IS DEVISED AND INTENDED FOR technology ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. The international technology roadmap for semiconductors : 2011 international technology roadmap for semiconductors 2011 Edition( 2011 ) ITRS STRJ JEITA ITRS STRJ 15 WG: Working Group ITRS 20 1000 ITRS STRJ ITRS ITRS ITRS 2005 ITRS 2007 ITRS ITRS 2009 ITRS ITRS Microsoft Excel ITRS STRJ JEITA STRJ ITRS

2 ITRS ITRS ITRS Executive Summary Acknowledgments ITRS ITRS( international technology roadmap for semiconductors ) ITRS: international technology roadmap for semiconductors ITRS international technology roadmap for semiconductors Executive Summary Glossary ITRS The international technology roadmap for semiconductors .

3 2011 JEITA SRTJ ITRS ITRS STRJ 2012 5 JEITA STRJ ORIGINAL (ENGLISH VERSION) COPYRIGHT 2011 SEMICONDUCTOR INDUSTRY ASSOCIATION All rights reserved ITRS SEMATECH, Inc. , 257 Fuller Road, Albany, NY 12203 Japanese translation by the JEITA, Japan Electronics and Information technology Industries Association under the license of the Semiconductor Industry Association ( ) ITRS 2011 Edition page XX, Figure(Table) YY ITRS 2011 Edition JEITA XX , ( )YY ---------------------------------------- ------- : 03-5218-1068 : The international technology roadmap for semiconductors : 2011 TABLE OF CONTENTS 1.

4 1 2.. 2 .. 2 .. 4 .. 5 3. Nano-information Processing Taxonomy .. 5 4. EMERGING RESEARCH DEVICES .. 6 Memory Taxonomy and DEVICES .. 6 .. 17 MORE-THAN-MOORE 32 5. EMERGING RESEARCH Architectures .. 36 EMERGING Memory Architectures in Conventional Computing .. 36 Evolved Architectures Exploiting EMERGING RESEARCH Memory 40 .. 41 6.. 46 .. 46 CMOS .. 46 BEYOND CMOS .. 51 .. 53 .. 59 7.. 61 .. 61 61 LIST OF FIGURES Figure ERD1 Relationship among More Moore, More-than-Moore, and Beyond 2 Figure ERD2 A Taxonomy for EMERGING RESEARCH Information Processing DEVICES (The technology entries are representative but not comprehensive.)

5 6 Figure ERD3 Schematic layout of the excitonic field-effect transistor (ExFET).. 1 Figure ERD4 A Taxonomy for EMERGING RESEARCH Information Processing DEVICES (The technology entries are representative but not comprehensive.).. 33 Figure ERD5 Median delay, energy, and area of proposed DEVICES , normalized to ITRS 15-nm CMOS. (Based on principal investigators data; from Rev.. 48 The international technology roadmap for semiconductors : 2011 Figure ERD6 Energy versus delay of a NAND2 gate in various post-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS are included as reference. All values are a snapshot in time, and will change as work continues. (Based on principal investigators data; from Ref. ).. 49 Figure ERD7 Inverter energy and delay and interconnect delay (*characteristic of transport over 10um) for various beyond-CMOS technologies.)

6 Projections for both high-performance and low-power 15nm CMOS included as reference. Solid dots indicate the switch is intrinsically non-volatile. All values are a snapshot in time, and will change as work continues. (Based on principal investigators data)49 Figure ERD8 Transport impact on switch delay, size, and area of control. Circle size is logarithmically proportional to physically accessible area in one delay. Projections for 15nm CMOS included as reference. (Based on principal investigators data; from Ref. ).. 50 Figure ERD10 a-f technology Performance Evaluation for a) Redox Resistive Memory, b) Ferroelectric Memory, c) Nanomechanical Memory, d) Mott Memory e) Macromolecular Memory, and f) Molecular 58 Figure ERD 11 a-f technology Performance Evaluation for a) Nanowire MOSFETs, b) CNT MOSFETs, c) GaInSb and GaSbP p-channel MOSFETs, d) Ge and InP n-channel MOSFETs, e) GNR MOSFETs, and f) Tunnel MOSFETs.

7 58 Figure ERD 12a-d technology Performance Evaluation for a) I MOSFET, b) Ferroelectric Negative Cg MOSFET, c) Atomic Switch, and d) Mott 58 Figure ERD 12e-g technology Performance Evaluation for e) Spin FET and Spin MOSFET, f) NEMS Device, and g) P/N Junction 58 Figure ERD13a-f technology Performance Evaluation for a) BiSFET, b) Exciton FET, c) Spin Torque Majority Gate, d) All Spin Logic Device, e) Spin Wave Device, and f) Nanomagnetic Logic 58 LIST OF TABLES Table ERD1 EMERGING RESEARCH DEVICES Difficult Challenges .. 3 Table ERD2 Memory 6 Table ERD3 Current Baseline and Prototypical Memory 7 Table ERD4 Transition Table for EMERGING RESEARCH Memory 7 Table ERD5 EMERGING RESEARCH Memory DEVICES Demonstrated and Projected Parameters 7 Table ERD6 Experimental Demonstrations of Vertical Transistors In Memory Arrays.

8 8 Table ERD7 Benchmark Select Device 8 Table ERD8 Experimentally Demonstrated 2-Terminal Select 8 Table ERD9 Target device and System Specifications for 8 Table ERD10 Potential of the Current Prototypical and EMERGING RESEARCH Memory Candidates for SCM Applications .. 8 The international technology roadmap for semiconductors : 2011 Table ERD11 Transition Table for EMERGING RESEARCH Logic 18 Table ERD12a MOSFETS: Extending MOSFETs to the End of the 18 Table ERD12b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based Information Carrier 18 Table ERD12c Alternative Information Processing DEVICES .. 18 Table ERD13 Anticipated Important Properties of EMERGING Memories as driven by Application Need 40 Table ERD14 Likely desirable properties of M (Memory) type and S (Storage) type Storage Class Memories 40 Table ERD15 Current RESEARCH Directions for Employing EMERGING RESEARCH Memory DEVICES to Enhance 40 Table ERD16 Applications and Development of Neuromorphic System.

9 41 Table ERD17 Noise-Driven Neural Processing and its Possible Applications .. 42 Table ERD18 Potential Evaluation for EMERGING Reseach Memory 54 Table ERD19 Potential Evaluation - Extending MOSFETS to the end of the 54 Table ERD20 Potential Evaluation - Non-conventional FETs and other Charge-based Devices54 Table ERD21 Potential Evaluation: Non-FET, Non-Charge-Based "Beyond CMOS" Devices54 The international technology roadmap for semiconductors : 2011 Emarging RESEARCH DEVICES 1 EMERGING RESEARCH DEVICES 1. CMOS CMOS CMOS "More than Moore heterogeneous integration ERD EMERGING RESEARCH device ITRS CMOS CMOS ERD ERD / ITRS More-than-Moore (MtM)

10 2 1) CMOS 2) Figure ERD1 CMOS More Moore CMOS ERD More-than-Moore Beyond CMOS ERD Beyond CMOS More-than-Moore More Moore CMOS Extended CMOS The international technology roadmap for semiconductors : 2011 2 Emarging RESEARCH DEVICES Figure ERD1 Relationship among More Moore, More-than-Moore, and Beyond CMOS. ERD 4 1) 2) 3) 4) CMOS CMOS More-than-Moore Strage Class Memory Solid State Drive Memory crossbar memory / Select Device/Diode CMOS 2009 2 RAM Spin Transfer Torque Magnetostatic RAM.