EnDat 2.2 System Reference Design - Texas Instruments

1 Application, RTOS, Communication Stack &FOC Position/ Velocity Control LoopCortex A9 NEON+VFPv3timing masterEOC InterruptPLC MasterEtherCAT Sync0 InterruptPDI InterruptEncoderMDRV8313 CurrentMsmtICSS-1 PRU0+PRU1 Real Time EthernetEtherCATPRU0 Position FeedbackEnDAT Chip Current SensePWMP ositionMsmtSitara AM437xICSS-0TI SystemReferenceDesignTI DesignsDesignFeaturesTI Designsprovidethe foundationthat you need EnablesDevelopersto Use Encoderincludingmethodology,testingand designfiles toInterlacesto Implementa Low FootPrint,Low-quicklyevaluateand customizethe DesignsPowerSingle-ChipSolutionsin ApplicationsSuchhelpyouaccelerateyourtim e to IndustrialAutomationand FactoryAutomation.

2 Providesan InterfaceThatis the TechnicalDesignResourcesStandardfor DirectDriveTechnologyThanksto itsHigh-Resolution,ShortCycleTimes,Commu tationToolFolderContainingDesignFilesTID EP0050 Information,LongLine LengthSupport,andSitaraProcessorsProduct FolderEncoderDiagnosticsAM437xISDKP roductFolder FeaturesSimpleDigitalConnectionTechnolog y,and SimpleVoltage-SupplyRequirementsThatRedu cesOverallSystemCostASKOur E2E Experts Basedon Sitara AM437xProcessorWhichWEBENCH CalculatorToolsSupportsSingle-ChipMotorC ontrolApplicationsand OtherEmbeddedControland CommunicationsApplications SitaraAM437xSupportsa Numberof IndustrialCommunicationsStandardsIncludi ngEtherCAT ,PROFINET , PROFIBUS,EtherNet /IP ,PowerLink,and SercosFeaturedApplications Master IndustrialDrives IndustrialSensorsand I/O ModulesSitara,IP.

3 CodeComposerStudioare trademarksof a registeredtrademarkof a registeredtrademarkof a registeredtrademarkof a registeredtrademarkof a registeredtrademarkof a registeredtrademarkof othertrademarksare the propertyof 2015, IMPORTANTNOTICEat the end of this TI referencedesignaddressesauthorizeduse, intellectualpropertymattersand otherimportantdisclaimersand TI Designimplementsthe Masterprotocolstackand hardwareinterfacesolutionbasedonthe standardfor positionor designis composedof Masterprotocolstack,half-duplexcommunica tionsusingRS-485transceiversand the lineterminationimplementedon the SitaraAM437xIndustrialDevelopmentKit (IDK).This designis fullytestedto meetthe EnDatpositionfeedback,the AM437xIDK also supportsindustrialcommunicationsand motordriveas describedin theAM437xSingle-ChipMotor-ControlDesignG uide(TIDU800).

4 September2015 SubmitDocumentationFeedbackCopyright 2015, OverviewEnDatstandsfor supportstreamlinedfactoryautomationproce sses,industrialdriveswith positionfeedbackrequiresaccurate,high-re liability,and interfaceprovidesall of interfaceis a digital,bidirectionalinterfacestandardfo r incrementaland EnDatinterfacesupportsthe transmissionof positionand auxiliaryvaluesfroman encoderas well as transmittingorupdatinginformationstoredi n the encoder ,or savingnew interfacethe EnDatMaster,or subsequentelectronics,usesmodecommandsto readencoderpositionvalues,additionalenco derphysicalvalues,parameters,and the internalmemoryof the encoder ,or to writeto the memoryofthe encodertype is containedin the encoder smemoryareaof the typesare.

5 Incrementallinearencoder Absolutelinearencoder Rotationalincrementalsingle-turnencoder Rotationalabsolutesingle-turnencoder Multiturnrotaryencoder Multiturnrotaryencoderwith batterybufferThe interfaceusesan 8-wireshieldedcable,as shownin Figure1 to connectthe positionencoderto the interfacecontainsa serialcommunicationsis composedof a differentialbidirectionaldata(DATA+andDA TA ) and a differentialclock(CLOCK+and CLOCK ) that is generatedby the bidirectionaldateis transmittedsynchronouslywith the the ,the receiveddatais latchedon the clockremainshigh whendatais not beingtransmittedor othertwo wiresare usedfor batterybufferingoras parallelpowersupplylinesto reduceIR Encoderand SubsequentElectronics3 TIDUAL5 2015,TexasInstrumentsIncorporatedTminTmi nMaximum pulse frequencyCmin1F(2 t)

6 Minimumpermissibleclockpulsefrequencyis 100 kHz,and the maximumpossibleclockpulsefrequencyis 2 ,the maximumpermissibleclockpulsefrequencydep endson the cablelengthbetweenthe encoderand the showsthemaximumpermissibleclockpulsefreq uency,Fc, with respectto the cablelengthbetweenthe encoderand the subsequentelectronicswhenan on-offratioof 1:1 is usedfor the MaximumClockFrequenciesvs CableLengthfor the WithoutDelayCompensationFor all otherratios,the maximumfrequenciesis determinedby the smallesthigh or low clockpulseperiod(seeFigure3).Figure3. September2015 SubmitDocumentationFeedbackCopyright 2015, the cablelengthincreaseswith high clockpulsefrequencies,the propagationtime betweentheencoderand subsequentelectronicsbecomeslargeenought hat delaycompensationmustbe employedto performedby the subsequentelectronicsonthe datathat is receivedfromthe compensationis performedby determiningthepropagationtime and compensatingfor the delayof the receivedencoderdatafromthe compensationis ,a maximumclockpulsefrequencyof 8 MHzis possiblefor cablelengthsof up to 100 m.

7 Clockfrequenciesfrom8 to16 MHzare intendedfor showsthe maximumclockfrequenciesvs cablelengthfor the MaximumClockFrequenciesvs CableLengthfor the propagationtime is recomputedby the subsequentelectronicswhenevera hardwarechangeisdetected,or immediatelyaftera propagationdelayis measuredusinga 100 achieveaccuracy,the delaymeasurementis performedusinga samplingfrequencythat is higherthanthe intendeddatatransmissionmaximumintendedc lockfrequency,Fc, with amaximumvariationof less than 10%.The delaymeasurementis performedby the subsequentelectronicsissuing"Encodersend positionvalues" encodertransceiverhas switchedto sending,after10 clockpulseperiods,the subsequentelectronicsstartsa counterto measurethe delaymeasurementiscapturedwhenthe risingedgeof the startbit is delaymeasurementat leastthreetimesand computethe validmeasurementoccurswheneachmeasuredde layvalueis within1/8of the periodof the maximumintendedclockpulsefrequency,Fc.

8 Figure5 showsthe DelayMeasurement5 TIDUAL5 2015, :If the maximumclockpulsefrequencyfor laterdatatransmissionis 4 MHz(Fc = 4 MHz) choosea samplingfrequencyof 4 MHz 8 = 32 MHzor maximumpermissiblevariationof thesamplingfrequencyis 10%or the delaymeasurementsto be valid,eachdelaymeasurementmustbe within1 / (4 MHz)/ 8 = of the avoida collisionon the dataline whendatatransmissionwith delaycompensationis active,a low levelmsutbe maintainedfor tSTfor the first clockcyclefor valueof tSTshouldbe in therangefrom2 to 10 s and is dependentuponline lengthand EnDatTimingAt the conclusionof the datatransmission,the clockmustbe set HIGHfor the recoverytime,tM.

9 Therecoverytime is a selectableparameterthat can be 10 to 30 s or s . Thenfollowinganadditionaldelay,tRof up to 500 ns, a new transmissioncan be showsthe TimingPARAMTERSYMBOLWITHOUTDELAYCOMPENSA TIONWITHDELAYCOMPENSATIONC lockFrequency()fc100 encoders: sfor msParamater10 to 30 s or s ( > 1 MHz)tm(configurable) nstST2 s to 10 + (cablelengthin m) sAdditionalinformationon the interfaceis availablein September2015 SubmitDocumentationFeedbackCopyright 2015, TI Designimplementsthe Masterprotocolstackand hardwareinterfacesolutionbasedonthe standardfor positionor TI designdrawsuponthe TIAM437xIndustrialDevelopmentKit (IDK)to providethe physicalhardwarecomponentsand theSYS/BIOSI ndustrialSoftwareDevelopmentKit (SDK)

10 For Sitarato providethe Masterprotocolstackand the firmwaresupportingthe AM437xIDK and SDKalso supportindustrialcommunicationsand motordrivewith currentfeedbackas describedin the AM437xSingle-ChipMotor-ControlDesignGuid e(TIDU800). Figure7 showsa simplifiedblockdiagramof the AM437xIDKand its interfaceto a digitalencoderalongwith otherfunctionsfor industrialcommunicationsand showsthe TIDEP0050 SystemBlockDiagramThe majorbuildingblocksimplementingthe Masterinterfaceare the AM437x,RS-485transceivers,the encoderpowersupply,and the line AM437xIndustrialDevelopmentKit7 TIDUAL5 2015, AM437xArchitectureThe SitaraAM437xfamilycontainsa Cortex -A9 processorwith NEONand VFPv3plus a powerfulset ofprogrammableand fixed-functionperipheralsfor industrialcommunications,measurement,and peripheralset includesthe pulsewidthmodulators(PWMs),analog-to-dig italconverters(ADCs)