Enhanced Host Controller Interface Specification …

1 Enhanced host Controller Interface Specification for universal serial Bus Date: March 12, 2002 Revision: EHCI Revision 3/12/2002 USB THIS Specification IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, Specification OR SAMPLE. Information in this Specification is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein, except that a license is hereby granted to copy and reproduce this Specification for internal use only. Contact Intel for information on further licensing agreements and requirements.

2 Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this Specification . Except as provided in Intel s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to documents, specifications and product descriptions at any time, without notice.

3 Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest documents and/or specifications, and before placing any product order. Copies of documents which have an ordering number and are referenced in this Specification , or other Intel literature, may be obtained from: Intel Corporation or, call 1-800-548-4725 Copyright Intel Corporation 1999 2001 * Third-party brands and names are the property of their respective owners.

4 EHCI Revision 3/12/2002 USB Revision History Revision Issue Date Comments 7/20/1999 Initial Revision 8/10/1999 Added information in data structures to support split transactions, etc. Started adding information into operational model (Chapter 4). rc1 12/21/1999 Significant additions to complete definition for register space, data structures and operational model. rc2 1/3/2000 Updated based on feedback. rc5 1/12/2000 Updated based on rc2 feedback. Internal, incremental revisions account rcX jump. 1/13/2000 Editorial changes from rc5. 7/6/2000 Update for yellow cover release. Also includes additions for debug port. rc1 9/26/2000 Editorial updates. Deleted Chapter 5, Legacy Keyboard. 11/10/2000 Final editorial updates.

5 Rc1 4/23/2001 Editorial clarifications; Fix for erratum on handling CErr during Interrupt split transactions and new features for managing frame- wrap FS/LS interrupt, Asynchronous Park-mode, FS/LS Rebalancing and new EHCI ownership semaphores. 5/30/2001 Fixed numerous typos, relaxed requirements on park mode, added CErr handling for FS/LS Setup transactions and numerous other clarifications. 6/12/2001 Added requirement to handling of full-speed isochronous-IN data streams (for compatibility). 6/20/2001 Final editorial edits, pagination, etc. rc1 1/31/2002 Editorial changes accumulated from industry feedback. 3/13/2002 Editorial changes accumulated during Licensee Review Period. NOTE TO SOFTWARE DEVELOPERS: Revisions of the EHCI Specification have introduced new features in the programming Interface .

6 Software must not attempt to use features defined in recent revisions of the Specification on host controllers designed to older revisions. A summary of new features, per revision is provided below. Revision Software-visible New Feature Frame Span Traversal Nodes (FSTN), see Section Rebalance Lockout (I-Bit), see Sections , Asynchronous Park Mode, see Sections , , and EHCI Extended Capabilities, see Section 5. Legacy Support, see Section EHCI Revision 3/12/2002 USB Significant Contributors: John S. Howard Intel Corporation Nobuo Furuya NEC Darren Abramson Intel Corporation James E. Guziak Lucent Michael N. Derr Intel Corporation Brian Leete Intel Corporation John Garney Intel Corporation Brad Hosler Intel Corporation Karthi Vadivelu Intel Corporation Chris Robinson Microsoft Ken Stufflebeam Compaq Please send comments via electronic mail to: EHCI Revision 3/12/2002 USB Page intentionally left blank EHCI Revision 3/12/2002 USB i Table of Contents 1.

7 INTRODUCTION .. 1 EHCI Product Compliance .. 2 Architectural Overview .. 2 Interface Architecture .. 4 EHCI Schedule Data Structures .. 5 Root Hub Emulation .. 5 2. REGISTER Interface .. 7 PCI Configuration Registers (USB) .. 8 PWRMGT PCI Power Management Interface .. 8 CLASSC CLASS CODE REGISTER .. 9 USBBASE Register Space Base Address Register .. 9 SBRN serial Bus Release Number Register .. 9 Frame Length Adjustment Register (FLADJ) .. 10 Port Wake Capability Register (PORTWAKECAP) .. 11 USBLEGSUP USB Legacy Support Extended Capability .. 11 USBLEGCTLSTS USB Legacy Support Control/Status .. 12 host Controller Capability Registers .. 13 CAPLENGTH Capability Registers Length.

8 13 HCIVERSION host Controller Interface Version Number .. 14 HCSPARAMS Structural Parameters .. 14 HCCPARAMS Capability Parameters .. 15 HCSP-PORTROUTE Companion Port Route Description .. 16 host Controller Operational Registers .. 17 USBCMD USB Command Register .. 18 USBSTS USB Status Register .. 21 USBINTR USB Interrupt Enable Register .. 22 FRINDEX Frame Index Register .. 23 CTRLDSSEGMENT Control Data Structure Segment Register .. 24 PERIODICLISTBASE Periodic Frame List Base Address Register .. 24 ASYNCLISTADDR Current Asynchronous List Address Register .. 25 CONFIGFLAG Configure Flag Register .. 25 PORTSC Port Status and Control Register .. 26 3. DATA STRUCTURES .. 31 Periodic Frame List.

9 31 Asynchronous List Queue Head Pointer .. 32 Isochronous (High-Speed) Transfer Descriptor (iTD) .. 33 Next Link Pointer .. 33 EHCI Revision 3/12/2002 ii USB iTD Transaction Status and Control List .. 34 iTD Buffer Page Pointer List (Plus) .. 35 Split Transaction Isochronous Transfer Descriptor (siTD) .. 36 Next Link Pointer .. 37 siTD Endpoint Capabilities/Characteristics .. 37 siTD Transfer State .. 38 siTD Buffer Pointer List (plus) .. 39 siTD Back Link Pointer .. 40 Queue Element Transfer Descriptor (qTD) .. 40 Next qTD Pointer .. 41 Alternate Next qTD Pointer .. 41 qTD Token .. 42 qTD Buffer Page Pointer List .. 45 Queue Head .. 46 Queue Head Horizontal Link Pointer .. 46 Endpoint Capabilities/Characteristics.

10 47 Transfer Overlay .. 49 Periodic Frame Span Traversal Node (FSTN) .. 51 FSTN Normal Path Pointer .. 51 FSTN Back Path Link Pointer .. 52 4. OPERATIONAL MODEL .. 53 host Controller Initialization .. 53 Port Routing and Control.. 54 Port Routing Control via EHCI Configured (CF) Bit .. 55 Port Routing Control via PortOwner and Disconnect Event .. 56 Example Port Routing State Machine .. 57 Port Power .. 57 Port Reporting Over-Current .. 58 Suspend/Resume .. 59 Port Suspend/Resume .. 59 Schedule Traversal Rules .. 61 Example - Preserving Micro-Frame Integrity .. 62 Periodic Schedule Frame Boundaries vs Bus Frame Boundaries .. 64 Periodic Schedule .. 66 Managing Isochronous Transfers Using iTDs.