Enhanced I2C and SMBus Master Interface …

1 Copyright 2016, Texas Instruments IncorporatedSMBus VSMBus slaveTIDEP0065AM437x1 TIDUBY1A July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016,TexasInstrumentsIncorporatedEnhance dI2 CandSMBusMasterInterfaceReferenceDesignW ithPRU-ICSSTI DesignsEnhancedI2C and SMBusMasterInterfaceReferenceDesignWithP RU-ICSSAll trademarksare the propertyof providesthe systemsolutionfor IndustrialCommunicationon Sitara processorswithprogrammablereal-timeunit and industrialcommunicationsubsystem(PRU-ICS S).PRU-ICSS allowscustomfirmwareapplicationsin the field of real-time I2C peripheralon manyapplicationprocessorsdoesnot supportSMBuscommandslike blockreadand TI DesignimplementsthoseSMBuscommandswith standardI2C commandsinto the TI Designsupports.

2 I2C and SMBusmasterinterfacewith PRU-ICSS Dynamicblockmodereadand writetransfer PRU-ICSS sourcecodefor customization(alreadyin the design)ResourcesTIDEP0065 DesignFolderAM4379 ProductFolderTMDSIDK437 XEVMT oolsFolderASKOur E2E ExpertsFeatures EnhancedI2C and SMBusMasterInterfaceExampleImplementatio n ValidatedWithTMDSIDK437 XIndustrialDevelopmentKit (IDK)EVM I2C RegisterInterfaceEmulationApplications ProgrammableLogicController(PLC) IndustrialI/O Modules IndustrialSensorand Actuators IndustrialEthernetAn IMPORTANTNOTICEat the end of this TI referencedesignaddressesauthorizeduse, intellectualpropertymattersand otherimportantdisclaimersand July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016, and SMBusThe systemmanagementbus ( SMBus )is derivedfroman inter-integratedcircuit(I2C) bus.

3 Varioussystemcomponentchipsand devicescan communicatethroughit. The SMBusis a two-wirepair interfacedevelopedby Intel in carriesclock,data,and instructionsthroughthis Interface ,and it supportsclockfrequenciesin the rangeof 10 to 100 SMBusprotocolis bidirectionalmaster-slavecommunicationpr otocol,whichcommunicateshalf duplexbecauseof a mastercommunicateswith the slaveby a protocolframeformatsthat theSMBussystemsupportsare QuickCommand,SendByte,ReceiveByte,WriteB yte/Word,ReadByte/Word,BlockWrite,and BlockRead all of theseprotocolcommandsare discussedin I2C BusThe differencesbetweenthe SMBusand I2C bus are.

4 Bothbusesoperatein the sameway up to 100 SMBuscannotoperatebeyond100 kHzwhereasthe I2C bus supportversionswith 400 kHz and 2 bothbusesis only ensuredif all devicesoperateat 100 kHz or below. The SMBussupportsa timeouteventwhereasI2C has no timeouteventis whentheslavedeviceresetsits interfacewheneverclockstayslongerthana certainperiodof time,typically35ms. In the I2C, the clockcan go staticfor indefiniteamountof time withoutthe occurrenceof a timeout. Timeoutdictatesthe minimumclockspeedspecification,so the minimumclockspeedfor SMBusis the I2C, thereis no suchrequirementand the clockspeedcan be DC.

5 The electricalspecificationfor the two busesare givenin Table1:Table1. ElectricalSpecificationsfor I2C and SMBusBUSV-HIGHV-LOWI-MAXI2C Bus3 V3 V350 AA deviceis compatiblewith bothbusesif its V-high> 3 V and V-low< V, and the pullupresistorvaluesare in the rangeof to k . I2C and SMBusbothsupportthe GeneralCall,whichis a specialslaveaddress(0b0000000).All slavedevicesdesignedfor GeneralCall will generalcall is a mechanismby whichcommunicationwith severalslavedevicessimultaneouslyis possible. SMBusalso supportsAlertResponse,whichI2C doesnot. SMBusprovidesa line calledALERTN umber,whichacts as interruptto the masterreceivesthis interrupt,itgeneratesan AlertResponse,whichis sent to slavedevicethatgeneratedthe interruptaftergettingthis responseputs its own addresson the bus to processuntil all generatedinterruptsare 2016, Texas Instruments IncorporatedSMBus VSMBus July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016, showsthe blockdiagramof the SMBussystem:Figure1.

6 To 1-GHzSitaraARM Cortex -A9 32 Bit RISCP rocessor NEON SIMDco-processorand vectorfloatingpoint(VFPv3)coprocessor 32 KBof L1 instructionand 32 KBof datacache 256 KBof L2 cacheor L3 RAM 256 KBof on-chipbootROM 64 KBof dedicatedRAM Emulationand debugJTAG InterruptcontrollerPRU-ICSS Supportsprotocolssuchas EtherCAT , PROFIBUS,PROFINET,EtherNet/IP , , and more Two PRUsubsystemswith two PRUcoreseach 32-bitload and storeRISC processorcapableof runningat 200 MHz 12KB(PRU-ICSS1),4KB (PRU-ICSS0)of instructionRAMwith single-errordetection(parity) 8KB (PRU-ICSS1),4KB (PRU-ICSS0)of dataRAMwith single-errordetection(parity) Single-cycle32-bitmultiplierwith 64-bitaccumulator EnhancedGPIO moduleprovidesshift-inand shift-outsupportand parallellatchon externalsignal 12KB(PRU-ICSS1only)of sharedRAMwith single-errordetection(parity) Three120-byteregisterbanksaccessibleby eachPRU Interruptcontrollermodule(INTC)

7 For handlingsysteminputevents Localinterconnectbus for connectinginternaland externalmastersto the resourcesinsidethe July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016,TexasInstrumentsIncorporatedEnhance dI2 CandSMBusMasterInterfaceReferenceDesignW ithPRU-ICSS Peripheralsinsidethe PRU-ICSS: One UART port with flow controlpins,supportsup to 12 Mbps One enhancedcapture(eCAP)module Two MII Ethernetportsthat supportindustrialEthernet,suchas EtherCAT One MDIO portOn-chipmemory(sharedL3 RAM) 256 KBof general-purposeon-chipmemorycontroller(O CMC)RAM Accessibleto all mastersExternalmemoryinterfaces(EMIF) DDRcontrollers: LPDDR2:266-MHzclock(LPDDR2-533datarate) DDR3and DDR3L.

8 400-MHzclock(DDR-800datarate) 32-bitdatabus 2 GBof total addressablespace Supportsone 32, two 16, or four 8 memorydeviceconfigurations General-purposememorycontroller(GPMC) Flexible8-bitand 16-bitasynchronousmemoryinterfacewith up to sevenchip selects(NAND,NOR,Muxed-NOR,SRAM) UsesBCHcodeto support4-, 8-, or 16-bitECC Useshammingcodeto support1-bitECCSee the AM4379datasheetfor a completelist of features(SPRS851). July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016, EVMH ardwareSpecification AM4379 ARMC ortex-A9 1 GBDDR3,QSPI-NORF lash Discretepowersolution EnDatconnectivityfor motorfeedbackcontrol 24-Vpowersupply USBcablefor JTAG interfaceand serialconsoleSoftwareand tools SYS/BIOS real-timeOS Starterwarebaseport CodeComposerStudio (CCS)integrateddevelopmentenvironment(ID E)

9 Applicationstackfor industrialcommunicationprotocols SampleindustrialapplicationsConnectivity PROFIBUS Interface CANOpen EtherCAT EtherNet/IP PROFINET SercosIII IEC61850 PWM Motoraxis positionfeedback Up to 3-phasemotordriveconnector Sigma-deltadecimationfilter Digitalinputsand outputs(I/O) SPI UART JTAGSee the AM437 XIDK websitefor a completelist of featuresand designresources( ).SAddressAWP1711 Data Byte81A1 SAddressAR/WP17111 SCLSDAS tart bitAddress bitsR/W bitACK bitStop July 2016 RevisedAugust2016 SubmitDocumentationFeedbackCopyright 2016, FrameFormatAll framesof the SMBusprotocolstartthe communicationon the bus whenthe masterassertsa startbitcondition(S).

10 The startbit is generatedwhenthe dataline is pulledto a low statefroma high statebymasterwhilethe clockline is at a high startbit is followedby 7 bits of slaveaddressappendedwith 1 bit for the slavesendsan ACK(A) to acknowledgeto the masterthat itwas addressedby the ACK,a commandcodeor datatransmissionof 8 bits canfollowfrommaster,whichis also acknowledgedby the communicationis terminatedwhenthemasterassertsa stop bit condition(P) on the bus. The stop bit is generatedwhenthe dataline is pulledtoa high statefroma low stateby masterwhilethe clockline is in a high startand stopbits, all transitionson the dataline happenduringthe durationof the clockwhenit is low.