ESD Layout Guide - Texas Instruments

1 1 SLVA680 February2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedESDP rotectionLayoutGuideApplicationReportSLV A680 February2015 ESDP rotectionLayoutGuideGuy systemagainstelectrostaticdischarge(ESD) is largelydependenton the printedcircuitboard(PCB) propertransientvoltagesuppressor(TVS)fou ndsthe basisof an ESDprotectionstrategy,its scopeis not availableinTechnicalDocumentsat guidancein choosingthe correcttypeof TVSdiodefor properTVSselected,designinga PCBL ayoutthat leveragesthe strategiesoutlinedin this ESDL ayoutGuidewill providethe PCBdesignerwithan avenuetowardssuccessfullyprotectinga OptimizingDissipationof ESDeventrapidlyforcescurrent(seeFigure1)

2 ,IESD, into a system,usuallythrougha userinterfacesuchas a cableconnection,or a humaninputdevicelike a key on a systemagainstESDusinga TVSreliesuponthe TVSbeingableto shuntIESDto PCBL ayoutfor ESDsuppressionis largelydependanton designingthe pathto groundforIESD with as littleimpedanceas ESDevent,the voltagepresentedto the protectedintegratedcircuit(ProtectedIC), VESD, is a functionofIESDand the impedancepresentedto it. Sincethe designerhas nocontroloverIESD, loweringthe impedanceto groundis the primarymeansavailablefor ,it cannotbe of zeroimpedance,or thesignalline beingprotectedwouldbe shortedto orderfor the circuitto havea realisticapplication,the protectedline needsto be ableto maintainsomevoltage,usuallyundera highimpedanceto is wherethe LineESD SourceProtected ICTVS0102030020406080100 Current (A)Time (ns)

3 IPEAK90%IPEAK10%IPEAK800 ps90/10 rise February2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedESDP rotectionLayoutGuideFigure1. IEC 61000-4-2 CompliantLevel4 (8 kV ESD)WaveformA TVSis an arrayof diodes(seeFigure2 for atypicalexample)arrangedto presenta very highimpedanceto the voltagesnormallypresentinthe circuit,but if voltagesexceedthe design,theTVSdiodeswill breakdownandshuntIESD togroundbeforeit can damagethe thenchallengedto lowerthe impedanceforIESD fromthe ESDS ourcethroughthe TVSto A February2015 SubmitDocumentationFeedbackCopyright 2015,TexasInstrumentsIncorporatedESDP rotectionLayoutGuideThe impedancepresentedtoIESDis a functionof any impedanceinherentwith the TVS(in the diodearrayand the packageof the TVS)

4 And the PCBL ayoutbetweenthe ESDS ourceand the TVSis generallydesignedto offeras low of an impedanceto groundforIESDas its overalldesignconstraintswill properTVSselected,a criticalphaseof the designis to lowertheimpedancein the PCBL ayoutbetweenthe ESDS ourceand the the rapidlychangingIESDis its associatedrapidlychangingelectromagnetic field (EM)causinginterference(EMI)to coupleontoothercircuitsof the especiallytrue inthe areabetweenthe ESDS ourceand the TVSshuntsIESDto ground,the tracebetweenthe TVSand the ProtectedIC shouldbe relativelyfree of ,unprotectedcircuitsshouldnotbe adjacentto an ESDprotectedcircuit's tracesbetweenthe ESDS ourceand the orderto keepEMI emissionsat a minimum,circuittracesbetweenthe ESDS ourceand the TVSshouldhavecornerswhichdo not exceed45 or, ideally,whichare curvedwith today's PCBL ayout,boardspaceis at a ,includingTVSs.

5 Are designedto be ,the densityof theirplacementon the PCBis routingleanheavilyuponVIAsfor maximizingthe densityto increasethe system's featureset whiledecreasingthe system's ,particularlyrelatedto layerswitchingandVIAs,playsan importantrole in shuntingIESDto groundthroughthe theProtectedIC can be inducedby the mannerin whichthe circuitis routedto the ,placinga VIAbetweenthe ESDS ourceandthe TVSis detrimental,but in somecircumstancesthe designeris forcedto do so. Evenin thesecircumstance,if properlydone,VESDcan stillbe minimizedat the criticalin chassisgroundfor the TVSthat isseparatedfromthe digitaland/oranaloggroundby it this reason,manydesignsuse one commongroundfor the necessaryfor the TVSto havesuccessin dissipatingIESD withoutincreasingVESD.

6 Electricalconnectionsto an earthgroundedchassis,like a PCBgroundedthrough-holefor a chassisscrew,immediatelyadjacentto the TVSgroundand the ESDS ource's ground( a connectorshield)provideasoundmethodology in keepinggroundshiftsat ProtectedICs to a a systemcannotutilizeachassisearthground,t ightlycoupledmultiplelayergroundplanesca n helpkeepgroundshiftsatProtectedICs to a summarizetheseparameters,successfullypro tectinga systemagainstESDincludes: Controllingimpedancesaroundthe TVSfor dissipatingESDcurrent,IESD Limitingthe effectsof EMI on unprotectedcircuits ProperlyusingVIAsto maximizeESDdissipationby the TVS Designinga groundingschemewhichhas very low impedancefor the TVSP rotected LineESD SourceProtected ICL1L2L3L4 PCBL ayoutGuidelinesfor OptimizingDissipationof February2015 SubmitDocumentationFeedbackCopyright 2015.

7 TexasInstrumentsIncorporatedESDP rotectionLayoutGuide2 PCBL ayoutGuidelinesfor OptimizingDissipationof DissipatingESDO utsideof controlledRLCvalues,PCBshaveinherentpara siticswhichcontributeto detrimentalto the functionalityof the importantparasiticto considerwhendesigninga circuitto dissipateESDis (seeNote1,below)VESD=Vbr_TVS+ RDYN(TVS)IESD+L(dIESD/dt), and the termdIESD/dtis verylarge,the forcedcurrentinan ESDeventwill causelargevoltagesto dropacrossany example,in an 8 kV ESDeventas specifiedby IEC 61000-4-2,thedIESD/dt= (30 A)/( 10-9s) = 4 1010A/s.

8 So evenwith of inductancean additional10 V is presentedto the : Vbr_TVSis the voltagerequiredfor theTVSto enterits breakdownregionandbeginshuntingIESDto ground. RDYN(TVS)refersto the resistancethroughthe TVSdiodearraywhileoperatingin the breakdownregionofthe IV PCBI nductancearounda Single-channelTVSIn Figure3 four parasiticinductorsare shown:L1andL2is the inductancein the circuitbetweenthe ESDS ource(typicallya connector)and the TVS,L3is the inductancebetweenthe TVSand ground,andL4isthe inductancebetweenthe TVSand the ProtectedIC.

9 Not consideringVIAs,the inductorsL1andL4aregenerallydependantupo ndesignconstraintssuchas ,IESDcan still be "steered" towardsthe TVSby makingL4muchlargerthanL1. This is accomplishedby placingthe TVSas nearto the ESDS ourceas the PCBdesignrulesallowwhileplacingthe ProtectedIC farawayfromthe TVS,for examplenearthe middleof the >>L1, helpingshunttheIESDto the TVSadjacentto the connectoralso mitigatesEMI fromradiatinginto the be presentin a stub betweenthe TVSand the line designpracticeshouldbe ProtectedLine shouldrun directlyfromthe ESDS ourceto the protectionPin of the TVS.

10 Ideallywithno VIAsin the inductoratL3representsthe inductancebetweenthe TVSand reducedas muchas possible,and perhapsrepresentsthe mostpredominantparasiticinfluencingVESD. The voltagepresentedto the node"ProtectedLine" will beVESD=Vbr_TVS+ IESDRDYN(TVS)+(L2+L3)(dIESD/dt). Thusthe PCBdesignerneedsto minimizeL3and eliminateL2. MinimizingL3iscoveredin MinimizingL1is coveredin and : Minimizeany inductancebetweenthe ESDS ourceand the pathto groundthroughthe TVS Placethe TVSas nearto the connectoras designrulesallow Placethe ProtectedIC muchfurtherfromthe TVSthanthe TVSis to the connector Do not use stubsbetweenthe TVSand the ProtectedLine.