Transcription of eXtensible Host Controller Interface for Universal Serial ...
1 eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Requirements specification May 2019 Revision 2 NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. CONTACT INTEL ON FURTHER LICENSING AGREEMENTS AND REQUIREMENTS. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
2 Copyright 2008-2019 Intel Corporation. All rights reserved. 3 Contents 1 Preface .. 25 Objective of specification .. 25 Scope of Document .. 25 Document Organization .. 25 References .. 26 Index .. 27 Terms and Abbreviations .. 29 Compliance .. 46 Documentation Conventions .. 46 Capitalization .. 46 Bold Text .. 46 Italic Text .. 46 Numbers and Number Bases .. 46 Implementation Notes .. 47 Word Usage .. 47 Pseudo Code .. 47 Other Notation .. 48 2 Introduction .. 49 Motivation .. 49 Goals .. 50 Key features .. 50 xHCI Product Compliance .. 52 3 Architectural Overview .. 53 Interface Architecture .. 56 xHCI Data Structures .. 59 Device Context Base Address Array .. 59 Device Context .. 59 Slot Context .. 60 Endpoint Context .. 61 Input Context .. 62 Rings .. 63 Transfer Request Block .. 64 Scatter/Gather Transfers .. 66 Control Transfers.
3 68 Bulk and Interrupt Transfers .. 69 Isoch Transfers .. 69 Command Interface .. 72 No Op .. 73 Enable Slot .. 73 Disable Slot .. 74 Address Device .. 74 Configure Endpoint .. 75 Evaluate Context .. 76 Reset Endpoint .. 76 4 Stop Endpoint .. 77 Set TR Dequeue 77 Reset Device .. 77 Force Event .. 77 Negotiate Bandwidth .. 77 Set Latency Tolerance Value .. 78 Get Port Bandwidth .. 78 Force Header .. 78 General Information .. 78 Root Hub Management .. 79 xHCI Device Enumeration .. 79 4 Operational Model .. 80 Command Operation .. 80 Host Controller Initialization .. 80 USB Device Initialization .. 83 Resetting a Root Hub Port .. 87 Device Slot Assignment .. 88 Device Slot Initialization .. 88 Address Assignment .. 89 Device Configuration .. 90 Setting Alternate Interfaces .. 91 Low-Speed/Full-Speed Device Support .. 93 Bandwidth Management.
4 94 Device Detach .. 94 Device Slot Management .. 94 Device Context Index .. 96 Slot Context Initialization .. 96 Slot States .. 97 USB Standard Device Request to xHCI Command Mapping .. 102 Command Interface .. 103 Command Ring Operation .. 104 No Op .. 107 Enable Slot .. 107 Disable Slot .. 109 Address Device .. 110 Configure Endpoint .. 115 Evaluate Context .. 126 Reset Endpoint .. 128 Stop Endpoint .. 133 Set TR Dequeue 141 Reset Device .. 143 Force Event (Optional Normative) .. 145 Negotiate Bandwidth (Optional Normative) .. 147 Set Latency Tolerance Value (LTV) (Optional Normative) .. 149 Get Port Bandwidth (Optional Normative) .. 150 Force Header .. 153 Get Extended Property (Optional Normative) .. 155 Set Extended Property (Optional Normative) .. 158 Doorbells .. 158 Endpoint .. 160 Endpoint Addressing .. 160 Endpoint Context Initialization.
5 161 Endpoint Context State .. 162 5 TRB Ring .. 166 Transfer Descriptors .. 168 Transfer Ring Management .. 169 Command Ring Management .. 178 Event Ring Management .. 179 Host Controller TRB Handling .. 189 Transfer TRBs .. 189 Errors .. 195 Events .. 204 IOC Flag .. 207 TRBs .. 208 TRB Template .. 208 Transfer TRBs .. 210 Event TRBs .. 222 Command TRBs .. 223 Other TRBs .. 228 Vendor Defined TRB Types .. 232 TD Usage Rules .. 233 240 xHCI Stream Protocol .. 241 Stream ID Management .. 246 Evaluate Next TRB (ENT) .. 250 Device Notifications .. 251 Latency Tolerance Message Handling .. 251 Function Wake .. 254 Managing Transfer Rings .. 254 General Scheduling Model .. 256 Periodic Transfer Ring Scheduling .. 258 Interrupt Transfer Ring Scheduling .. 266 Asynchronous Transfer Ring Scheduling .. 269 Suspend-Resume .. 276 Port Suspend.
6 278 Port Resume .. 279 Bandwidth Management .. 283 Bandwidth Negotiation .. 284 Bandwidth Domains .. 285 Interrupters .. 286 Interrupter Mapping .. 288 Interrupt Moderation .. 289 Interrupt Pin Support .. 293 Interrupter Target Identification .. 294 Interrupt Blocking .. 295 Transfer Definition and Attributes .. 296 No snoop .. 296 No Snoop and Relaxed Ordering for USB Traffic .. 297 Root Hub .. 298 Root Hub Port State Machines .. 298 Port Status Change 319 Connect Status Change Reporting .. 322 Port Power .. 323 Port 327 Port Test Modes .. 329 Port Routing and Control .. 329 6 Cold Attach Status .. 331 Port Speed .. 332 Scratchpad Buffers .. 334 PCI Express .. 335 Configuration sharing among PCI functions .. 336 Bus Master Enable (BME) .. 336 xHCI Extended Capabilities .. 336 Pre-OS to OS Handoff Synchronization .. 336 Debug Capability Operational Model.
7 339 Virtualization .. 340 Power Management .. 340 Power Wells .. 340 xHCI Power Management .. 341 PCI Power Management .. 345 USB Power Management .. 345 USB Link Power Management .. 346 Host Controller Management .. 358 Internal Errors .. 358 Port to Connector Mapping .. 359 USB Virtualization Based Trusted IO Management (USB VTIO) .. 362 VTIO Usage and Requirements .. 364 Management of DMA-ID Assignment .. 365 5 Register Interface .. 368 Register Conventions .. 369 Attributes .. 369 Power Well Considerations .. 371 PCI Configuration Registers (USB) .. 371 Type 0 PCI Header .. 371 Class Code Register .. 373 Serial Bus Release Number Register (SBRN) .. 373 Frame Length Adjustment Register (FLADJ) .. 374 Default Best Effort Service Latency (DBESL) .. 375 Default Best Effort Service Latency Deep (DBESLD) .. 376 PCI Power Management Interface .
8 376 Message Signaled Interrupts (MSI & MSI-X) Capability .. 377 PCI Express Capability .. 380 SR-IOV Extended Capability .. 380 Host Controller Capability 380 Capability Registers Length (CAPLENGTH) .. 381 Host Controller Interface Version Number (HCIVERSION) .. 381 Structural Parameters 1 (HCSPARAMS1) .. 382 Structural Parameters 2 (HCSPARAMS2) .. 383 Structural Parameters 3 (HCSPARAMS3) .. 384 Capability Parameters 1 (HCCPARAMS1) .. 385 Doorbell Offset (DBOFF) .. 387 Runtime Register Space Offset (RTSOFF) .. 388 Capability Parameters 2 (HCCPARAMS2) .. 389 Virtualization Based Trusted IO Register Space Offset (VTIOSOFF) 390 Host Controller Operational Registers .. 391 USB Command Register (USBCMD) .. 393 USB Status Register (USBSTS) .. 397 Page Size Register (PAGESIZE) .. 399 7 Device Notification Control Register (DNCTRL) .. 400 Command Ring Control Register (CRCR).
9 401 Device Context Base Address Array Pointer Register (DCBAAP) .. 403 Configure Register (CONFIG) .. 404 Port Status and Control Register (PORTSC) .. 405 Port PM Status and Control Register (PORTPMSC) .. 415 Port Link Info Register (PORTLI) .. 418 Port Hardware LPM Control Register (PORTHLPMC) .. 419 Host Controller Runtime Registers .. 422 Microframe Index Register (MFINDEX) .. 423 Interrupter Register Set .. 424 Doorbell Registers .. 429 VTIO Registers .. 432 VTIO Capability Register (VTIOCAP) .. 432 VTIO Common Assignment Register 1 (VTIOCA1) .. 433 VTIO Device Assignment Registers 1 to 8 (VTIODA{ }) .. 435 VTIO Interrupter Assignment Registers 1 to 32 (VTIOIA{ }) .. 436 VTIO Endpoint Assignment Registers 1 to 255 (VTIOEA{ }) . 437 6 Data Structures .. 439 Device Context Base Address Array .. 440 Contexts .. 442 Device Context .. 442 Slot Context.
10 444 Endpoint Context .. 449 Stream Context Array .. 457 Input Context .. 459 Port Bandwidth Context .. 463 Get Extended Property Context .. 464 TRB Ring .. 464 Transfer Request Block (TRB) .. 465 Transfer TRBs .. 465 Event TRBs .. 477 Command TRBs .. 487 Other TRBs .. 503 TRB Completion Codes .. 507 TRB Types .. 511 Event Ring Segment Table .. 514 Scratchpad Buffer Array .. 515 PSZ .. 516 7 xHCI Extended Capabilities .. 517 USB Legacy Support Capability .. 518 USB Legacy Support Capability (USBLEGSUP) .. 519 USB Legacy Support Control/Status (USBLEGCTLSTS).. 520 xHCI Supported Protocol Capability .. 521 Protocol Speed ID (PSI).. 524 Supported Protocols .. 525 HCI Extended Power Management Capability .. 531 xHCI Extended Message Interrupt Capability .. 531 xHCI Message Interrupt Capability .. 532 Debug Capability (DbC) .. 532 Debugging Topologies.
