External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP ...

1 External Memory Interfaces Intel Cyclone 10 gx FPGA IP User GuideUpdated for Intel Quartus Prime Design Suite: Version: FeedbackUG-20116 | document on the web: PDF | HTMLC ontents1. Release 72. External Memory Interfaces Intel Cyclone 10 gx FPGA IP Intel Cyclone 10 gx EMIF IP Design Intel Cyclone 10 gx EMIF IP Design Intel Cyclone 10 gx EMIF IP Product EMIF Architecture: I/O I/O I/O I/O I/O Input DQS Clock PHY Clock PLL Reference Clock Clock Phase Intel Cyclone 10 gx EMIF DQS Intel Cyclone 10 gx EMIF Calibration Stages .. Calibration Stages Calibration Calibration Intel Cyclone 10 gx EMIF Hard Memory Hard Memory Controller Rate Conversion Hardware Resource Sharing Among Multiple I/O Aux I/O Bank PLL Reference Clock Core Clock Network Intel Cyclone 10 gx EMIF Ping Pong Ping Pong PHY Feature Ping Pong PHY Ping Pong PHY Ping Pong PHY Using the Ping Pong Ping Pong PHY Simulation Example 404.

2 Intel Cyclone 10 gx EMIF IP End-User Interface and Signal Intel Cyclone 10 gx EMIF IP Interfaces for Intel Cyclone 10 gx EMIF IP Interfaces for AFI AFI Clock and Reset AFI Address and Command AFI Write Data Memory Interfaces Intel Cyclone 10 gx FPGA IP User GuideSend AFI Read Data AFI Calibration Status AFI Shadow Register Management AFI Timing AFI Address and Command Timing AFI Write Sequence Timing AFI Read Sequence Timing AFI Calibration Status Timing Intel Cyclone 10 gx Memory Mapped Register (MMR) ecc3: ECC Error and Interrupt ecc4: Status and Error ecc5: Address of Most Recent ecc6: Address of Most Recent Correction Command 885.

3 Intel Cyclone 10 gx EMIF Simulating Memory Simulation Simulation Calibration Abstract PHY Simulation Functional Simulation with Verilog Functional Simulation with Simulating the Design FeedbackExternal Memory Interfaces Intel Cyclone 10 gx FPGA IP User Guide36. Intel Cyclone 10 gx EMIF IP for Parameter Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Intel Cyclone 10 gx EMIF IP DDR3 Parameters: FPGA Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Mem Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Mem Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Intel Cyclone 10 gx EMIF IP DDR3 Parameters: Intel Cyclone 10 gx EMIF IP DDR3 Parameters.

4 Example Board Skew Equations for DDR3 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Cyclone 10 gx EMIF DDR3 Board Design Terminations and Slew Rates with Intel Cyclone 10 gx Channel Signal Integrity Layout Design Layout Package 1467. Intel Cyclone 10 gx EMIF IP for Parameter Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: FPGA Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Mem Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Mem Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters: Intel Cyclone 10 gx EMIF IP LPDDR3 Parameters.

5 Example Board Skew Equations for LPDDR3 Board Skew Pin and Resource Interface LPDDR3 Board Design Terminations and Slew Rates with Intel Cyclone 10 gx Channel Signal Integrity Layout Design Layout Package 1918. Intel Cyclone 10 gx EMIF IP Timing Timing Closure .. Timing Timing Report Optimizing Memory Interfaces Intel Cyclone 10 gx FPGA IP User GuideSend Early I/O Timing Performing Early I/O Timing Optimizing Controller Interface Bank Management Data Improving Controller Auto-Precharge Bank Additive Latency and Bank User-Controlled Frequency of Series of Reads or Data Starvation Command Enable Command Priority 22210.

6 Intel Cyclone 10 gx EMIF IP Interface Configuration Performance Interface Configuration Bottleneck and Efficiency Functional Issue Intel IP Memory Vendor Memory Transcript Window Modifying the Example Driver to Replicate the Timing Issue Evaluating FPGA Timing Evaluating External Memory Interface Timing Verifying Memory IP Using the Signal Tap II Logic Signals to Monitor with the Signal Tap II Logic Hardware Debugging Create a Simplified Design that Demonstrates the Same Measure Power Distribution Measure Signal Integrity and Setup and Hold Vary Operate at a Lower Determine Whether the Issue Exists in Previous Versions of Determine Whether the Issue Exists in the Current Version of Try A Different Try Other Debugging Categorizing Hardware Signal Integrity Hardware and Calibration Debugging Intel Cyclone 10 gx EMIF External Memory Interface Debug FeedbackExternal Memory Interfaces Intel Cyclone 10 gx FPGA IP User On-Chip Debug Port for Intel Cyclone 10 gx EMIF Efficiency Monitor and Protocol Using the Traffic Generator with the Generated Design External Memory Interfaces Intel Cyclone 10 gx FPGA IP User Guide Document Revision History for Intel Cyclone 10 gx External Memory InterfacesFPGA IP User 262 ContentsExternal Memory Interfaces Intel Cyclone 10 gx FPGA IP User GuideSend Feedback61.

7 Release InformationIP versions are the same as the Intel Quartus Prime Design Suite software versionsup to From Intel Quartus Prime Design Suite software version or later, IPcores have a new IP versioning IP versioning scheme ( ) number changes from one software version toanother. A change in: X indicates a major revision of the IP. If you update your Intel Quartus Primesoftware, you must regenerate the IP. Y indicates the IP includes new features. Regenerate your IP to include these newfeatures. Z indicates the IP includes minor changes. Regenerate your IP to include Quartus | FeedbackIntel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/orother countries.

8 Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 Registered2. External Memory Interfaces Intel Cyclone 10 gx FPGAIP IntroductionIntel's fast, efficient, and low-latency External Memory interface (EMIF) intellectualproperty (IP) cores easily interface with today's higher speed Memory can easily implement the EMIF IP core functions through the Intel Quartus Primesoftware.

9 The Intel Quartus Prime software also provides External Memory toolkitsthat help you test the implementation of the IP in the External Memory Interfaces Intel Cyclone 10 gx FPGA IP (referred to hereafteras the Intel Cyclone 10 EMIF IP) provides the following components: A physical layer interface (PHY) which builds the data path and manages timingtransfers between the FPGA and the Memory device. A Memory controller which implements all the Memory commands and protocol-level information on the maximum speeds supported by the External Memory interfaceIP, refer to the External Memory Interface Spec Cyclone 10 gx Protocol SupportThe Intel Cyclone 10 gx External Memory Interfaces IP provides DDR3 and LPDDR3external Memory protocol support for Intel Cyclone 10 gx GX Information Intel FPGA IP for External Memory Interfaces - Support Center Intel Cyclone 10 gx Core Fabric and General Purpose I/Os Intel Cyclone 10 gx EMIF IP Design FlowIntel recommends creating an example top-level file with the desired pin outs and allinterface IPs instantiated.

10 This enables the Intel Quartus Prime software to validatethe design and resource allocation before PCB and schematic sign following figure shows the design flow to provide the fastest out-of-the-boxexperience with the EMIF | FeedbackIntel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice.