Example: biology
F133 - whycan.com
- RGB interface up to 1920 x 1080@60fps - Dual link LVDS interface up to 1920 x 1080@60fps - 4-lane MIPI DSI up to 1920 x 1200@60fps - CVBS OUT interface, supporting NTSC and PAL format Video Input - 8-bit digital camera interface - CVBS IN interface, supporting NTSC and PAL format (only for F133-B) Analog Audio Codec
Tags:
Information
Domain:
Source:
Link to this page:
Documents from same domain
1/2.9’’ FHD CMOS Image Sensor Data Sheet
whycan.comIt provides RAW10 and RAW8 data formats with MIPI and DVP interface. It has a commonly used two-wire serial interface for host to control the operation of the whole sensor. 1.2 Features Standard optical format of 1/2.9 inch 2.8μm*2.8μm Output formats: Raw Bayer 10bit/8bit Power supply requirement: AVDD28: 2.7~2.9V(Typ.2.8V)
Related documents
i.MX 6Dual/6Quad Applications Processor Data Sheet for ...
www.nxp.com† Interface flexibility—Each processor supports connections to a variety of interfaces: LCD controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS display), dual CMOS sensor in terface (parallel or through MIPI ), …
Layout Design Guide - Toradex
docs.toradex.comapplication was the Flat Panel Display Link, LVDS became a synonymous for this interface. In this document, the term LVDS is used for the FPD-Link interface. MIPI Mobile Industry Processor Interface Alliance MDI Medium Dependent Interface, physical interface between Ethernet PHY and cable connector
![DATA SHEET [PRELIMINARY] NVIDIA Jetson Xavier NX …](/cache/preview/c/b/1/9/2/4/a/0/thumb-cb1924a0bc504e526ece10c38e4b6630.jpg)
DATA SHEET [PRELIMINARY] NVIDIA Jetson Xavier NX …
www.miivii.com10/100/1000 Gigabit Ethernet | Media Access Controller (MAC) Imaging 12 lanes (3 x4 or 6 x2 or 6 x1) MIPI CSI-2 | D-PHY 1.2 (2.5 Gb/s per pair, total up to 30 Gbps) Display Controller Two multi-mode (eDP/DP/HDMI) Serial Output Resources (SOR) eDP 1.4a | DP 1.4 | HDMI 2.0a/b Maximum Resolution (eDP/DP/HDMI): (up to) 3840x2160 at 60 Hz
LCDTFT display controller LTDC on STM32 MCUs ...
www.st.comThe display controller can be embedded either in the display module or in the MCU. • The display glass is driven by the display controller and is responsible to display the image that is composed of a matrix of pixels. A display is characterized by: – Display size (resolution): is defined by the number of pixels of the display that is
Rockchip RK3399 Datasheet
opensource.rock-chips.comSupport standby mode to auto-gating DDR controller clock for power save Support power down DDR controller and DDR PHY Support hardware-based DDR frequency scaling eMMC Interface Fully compliant with JEDEC eMMC 5.1and eMMC 5.0 …
Rockchip RK3288 Datasheet
opensource.rock-chips.comSpecial 2D hardware engine with MMU will maximize display performance and provide very smoothly operation. RK3288 has high-performance dual …