Failure Analysis (FA) Introduction (IC Failure Mode)

1 Failure ModeFailure ModeTung-Bao Lu1 of 29 Failure Analysis (FA) IntroductionFailure Analysis (FA) Introduction ((IC Failure Mode) IC Failure Mode) Failure ModeFailure ModeTung-Bao Lu2 of 29leadframechipgold wireEMCdie-padStructure of conventional packageStructure of conventional packagePhysical Failure (Structure)- Popcorn- Delamination- Crack (Package/Die)Electrical Failure (Connection)- Open- Short- Leakage- FunctionIn-Process Failure (Production)- Front-end (before molding)- Back-end (After molding)- Testing (FT/Burn-in)Reliability Failure (Qualification)- Temperature- Humidity- Pressure- VoltageFailure ClassificationFailure ModeFailure ModeTung-Bao Lu3 of 29 Failure Mechanism(1) Moisture absorption(L-1: 85oC/85%RH) (L-3: 30oC/60%RH)(2) Moisture vaporizationduring heating(Reflow, 235oC/10s)(3) Vapor force separating(delamination)(4) Popcorn forming(package crack)(collapsed void)popcornChipdie-padleadframecrackPop corn ( )Popcorn ( ) Failure ModeFailure ModeTung-Bao Lu4 of 29 TQFP package (bottom popcorn)FBGA package (top popcorn) Failure ModeFailure ModeTung-Bao Lu5 of 29leadframechipdie-padgold wireEMC(3) Die Attach(chip/pad)(1) Die surface(EMC/chip)(2) Leadframe(EMC/leadframe)(4) Pad bottom(pad/EMC)crackcrackDelamination ( )Delamination ( ) Failure ModeFailure ModeTung-Bao Lu6 of 29leadframechipdie-padgold wireEMCcrackcrackDie Crack ( )EMC Crack ( )Crack ( )Crack ( )

2 Failure ModeFailure ModeTung-Bao Lu7 of 29 Failure ModeFailure ModeTung-Bao Lu8 of 29 Assembly FlowAssembly FlowLappingDicingDie attachWire bondMoldingMarkingDejunk/TrimPlatingForm ingTestingPacking /ShipLeadframeCompoundInkSolder anodeTube/TrayLappingDicingILBP otting & CureTAB tapeResinMarkingTestingM/VDefect punchPacking/ShipInkReel/SpacerCON PackageCON PackageTCP PackageTCP PackageBondabilityFailure ModeFailure ModeTung-Bao Lu9 of 29 Shift bonding (short/leakage, W/B)Ball lifted (open, W/B)Ball over-bonding (short, W/B)Wiring Bondability (TSOP/BGA) Failure ModeFailure ModeTung-Bao Lu10 of 29 Wiring Bondability (TSOP/BGA)Ball neck broken (W/B) Ball neck crack (W/B)Heel broken (open, W/B)Heel broken (open, W/B) Failure ModeFailure ModeTung-Bao Lu11 of 29No bonding (open, ILB)Poor bonding (open, ILB)Thin bump (open, ILB)Thin lead (open, ILB)Inner Lead Bondability (TCP/COF) Failure ModeFailure ModeTung-Bao Lu12 of 29 Alloy bubble (short, ILB ) IL shifted (short, ILB)Metal bridged (short, ILB)Bump crush (short, ILB)Inner Lead Bondability (TCP/COF) Failure ModeFailure ModeTung-Bao Lu13 of 29(function -> Leakage -> Short)SiO2 layer is damagedNormal bondabilitydamagedAfter crating testingKNO3 solution etchingRemove gold-ball bondingInspect Al-padBondability (Bonding Force) Failure ModeFailure ModeTung-Bao Lu14 of 29X-RAY Inspection (NDT)

3 2nd BondingBrokenFailure ModeFailure ModeTung-Bao Lu15 of 29 Open FailureForeign insulator stuck on leadPin- 1 Pin- 1 Chip damaged to impact the wire-4000-2000020004000 TiFTiNCOA lSi16001200500 DQ2 DQ13 DQ15C ountsK inetic Energy (keV )-3 00 0-2 00 0-1 00 001 00 02 00 0 AlSi DQ2 DQ1 3 DQ1 5C oun tsEnerg y-600-400-2000200400600 TiNTi D Q2 D Q13 D Q15 CountsEnergyPad contamination by Auger SpectrumInner wire neck brokenFAlAuFailure ModeFailure ModeTung-Bao Lu16 of 292nd bond liftedpin29 Open bonding is not easily detected by XRMH owever, after EMC decapsulation, 2nd bonding lifted is exposed by optical microscopeTSOPII 54L LOC(in-process open failed)(X-Ray Microscope)(Optical Microscope, 40X)Au-wireLead-frame2nd-bonding liftedOpen FailurePLCC 32L(Reflowing open failed)(SAT C-SCAN, die surface)Open bonding is not easily detected by XRMbonding lifted is exposed by SEM(SEM, 300X) Failure ModeFailure ModeTung-Bao Lu17 of 29 Open FailureSEM found concave andmicro-crack (1800x)Output Y41 Output Y41+-TapeDC test open (Fail)Bending TestBending TestVibration TestVibration TestSEM observed output lead broken (2000x)

4 ACF areaTFT PanelOpen positionFailure ModeFailure ModeTung-Bao Lu18 of 29 Open FailureTCP ProductInner Lead Bonding BrokenTCP ProductResin Cause BrokenTCP ProductInner Lead Peeling Failure ModeFailure ModeTung-Bao Lu19 of 29 Short FailureOver-compressed bondingShifted bondingSplit epoxy between leadframeChip circuit burn out Failure ModeFailure ModeTung-Bao Lu20 of 29 After PCT tests, solder growthUnloading from PCB, solder bridgedShort FailureWire lay on substrate finger to shortSn whisker to connect two pinsFailure ModeFailure ModeTung-Bao Lu21 of 29(Jay A. Brusse)(Compressive Stress)Short Failure (Tin Whisker) Failure ModeFailure ModeTung-Bao Lu22 of 29 Short FailureSn over-plating to lead short on tapeNeedle-like Sn grow to short while bondingAu pad bubble to short while bondingChip scratched to cause circuit shortFailure ModeFailure ModeTung-Bao Lu23 of 29 Leakage FailureTop Temperature = crackCorner ChippingIC Circuit burn-outCorner die crackFailure ModeFailure ModeTung-Bao Lu24 of 29 Function FailureCorner chippingSide chippingChip surface scratchAssembled Related Machine/Man DamagedFailure ModeFailure ModeTung-Bao Lu25 of 29 Particle damaged (~20um)Particle damaged (~10um)Assembled Related Environment (Particle Damaged)

5 Function FailureFailure ModeFailure ModeTung-Bao Lu26 of 29D-company, EOS/ESD wiring burn-out to shortESD Cases of Driver ICsH-company, internal burn-out to short, ESD under pad( ~ ) Failure ModeFailure ModeTung-Bao Lu27 of 29 Appearance ofdamage (tendency)The location of damage is very small and cannot be identified by visually examiningthe semiconductor chipIf the energy of EOS is large of damage, such as breaks in wiring on the chip due to melting, discoloration, and burning of the package, can be the energy is small, it is difficult to distinguish damage caused by EOS from that caused by ESDP rocess of failureElectric charge damages the IC chip of semiconductor device when it discharges through the deviceA semiconductor device is damaged by application of an overvoltage or overcurrent while the device is operating (while the characteristics of the device are being used by the user)

6 Cause of failureDischarge due to contact of a charged body with the pins of a semiconductor device or discharge of an electric charge that takes place in the device itself because of friction or other causesGeneration of Latch-up, surge due to turning power on or offand measuring instruments on or off., short-circuit of the load, solder chips, and patterns short-circuit by metallic foreign objects. Photograph of chipSource: NEC information (1997, Guide to prevent damage for semiconductor devices by electrostatic discharge (ESD)) Difference between ESD and EOS(ESD)(EOS)EOS = Electrical Over StressESD = ElectroStatic DischargeFailure ModeFailure ModeTung-Bao Lu28 of 29 Major Mode of Damages by ESD(1) Damage to oxide film(2) Junction destruction (3) Melting of wiring film(Gate oxide failed)(Junction Breakdown)(Wiring burn-out)- Reverse bias- Current concentration- Shallow is easy- Gate film is only 10nm- Thin is easy- Thermal destruction- ESD (fine Al wiring is melted)EOS (coarse Al wiring)- Thin is easy Source: NEC information (1997, Guide to prevent damage for semiconductor devices by electrostatic discharge (ESD)) IC design trend:1.

7 Gate film is thinner2. Junction is shallower3. Al wiring is thinner=> On-chip protectioninternal ESD protectionFailure ModeFailure ModeTung-Bao Lu29 of 29 Structure/PropertyMaterialProcess