FIFO Intel® FPGA IP User Guide

1 FIFO intel FPGA IP User GuideUpdated for intel Quartus Prime Design Suite: VersionSend FeedbackUG-MFNALT_FIFOID: 683522 Version: intel FPGA IP User 3 Configuration HDL Component LIBRARY-USE Parameter Functional Timing 11 SCFIFO ALMOST_EMPTY Functional 12 FIFO Output Status Flag and Metastability Protection and Related Synchronous Clear and Asynchronous Clear and Removal Timing Violation Warnings when Compiling a and DCFIFO Show-Ahead Input and Output 20 DCFIFO Timing Constraint Timing Configurable Timing Example for Manual Counter Transfer at the Clock Domain for Embedded Memory ECC intel FPGA IP User Guide Revision History for the FIFO intel FPGA IP User intel FPGA IP User GuideSend Feedback2 FIFO intel FPGA

2 IP User GuideIntel provides FIFO intel FPGA IP core through the parameterizable single-clock FIFO(SCFIFO) and dual-clock FIFO (DCFIFO) functions. The FIFO functions are mostlyapplied in data buffering applications that comply with the first-in-first-out data flow insynchronous or asynchronous clock specific names of the FIFO functions are as follows: SCFIFO: single-clock FIFO DCFIFO: dual-clock FIFO (supports same port widths for input and output data) DCFIFO_MIXED_WIDTHS: dual-clock FIFO (supports different port widths for inputand output data)Note: The term DCFIFO refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS functions,unless Information Introduction to intel FPGA IP CoresProvides general information about all intel FPGA IP cores, includingparameterizing, generating, upgrading, and simulating IP cores.

3 Creating Version-Independent IP and Platform Designer Simulation ScriptsCreates simulation scripts that do not require manual updates for software orIP version upgrades. Project Management Best PracticesGuidelines for efficient management and portability of your project and IP files. intel Agilex 7 Embedded Memory User GuideRefer to the FIFO intel FPGA IP section within the intel Agilex EmbeddedMemory User Guide for Agilex specific information. intel Stratix 10 Embedded Memory User GuideRefer to the FIFO intel FPGA IP section within the intel Stratix 10 Embedded Memory User Guide for Stratix 10 specific information. FIFO intel FPGA IP User Guide Archives on page 32 Provides a list of user guides for previous versions of the FIFO intel FPGA | FeedbackIntel Corporation.

4 All rights reserved. intel , the intel logo, and other intel marks are trademarks of IntelCorporation or its subsidiaries. intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with intel 's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by intel . intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.

5 *Other names and brands may be claimed as the property of :2015 RegisteredConfiguration MethodsTable MethodsYou can configure and build the FIFO intel FPGA IP core with methods shown in the following the FIFO parameter recommends using this method to build your FIFOI ntel FPGA IP core. It is an efficient way to configure andbuild the FIFO intel FPGA IP core. The FIFO parametereditor provides options that you can easily use to configurethe FIFO intel FPGA IP can access the FIFO intel FPGA IP core parametereditor in Basic Functions On Chip Memory FIFO ofthe IP catalog.(1)Manually instantiating the FIFO intel FPGA IP this method only if you are an expert user.

6 This methodrequires that you know the detailed specifications of the IPcore. You must ensure that the input and output ports used,and the parameter values assigned are valid for the FIFOI ntel FPGA IP core you instantiate for your target InformationIntroduction to intel FPGA IP CoresProvides general information about the intel Quartus Prime Parameter EditorSpecificationsVerilog HDL PrototypeYou can locate the Verilog HDL prototype in the Verilog Design File (.v) the < intel Quartus Prime installation directory>\eda\ Component DeclarationThe VHDL component declaration is located in < intel Quartus Primeinstallation directory>eda\fv_lib\vhdl\megafunctions\ LIBRARY-USE DeclarationThe VHDL LIBRARY-USE declaration is not required if you use the VHDL altera_mf;USE ;(1)Do not use dcfifo or scfifo as the entity name for your FIFO Platform Designer intel FPGA IP User Guide683522 | intel FPGA IP User GuideSend Feedback4 FIFO SignalsThis section provides diagrams of the SCFIFO and DCFIFO blocks of the FIFO IntelFPGA IP core to help in visualizing their input and output ports.

7 This section alsodescribes each port in detail to help in understanding their usages, functionality, orany restrictions. For better illustrations, some descriptions might refer you to a specificsection in this user and DCFIFO Input and Output SignalsSCFIFO data[ ]wrreqrdreqsclraclrclockalmost_fullalmos t_emptyusedw[ ]emptyfullq[ ]DCFIFO data[ ]wrreqrdreqwremptyaclrrdemptyrdusedw[ ]wrclkwrusedw[ ]q[ ]rdfullwrfullrdclkeccstatus[1:0]eccstatu s[1:0]For the SCFIFO block, the read and write signals are synchronized to the same clock;for the DCFIFO block, the read and write signals are synchronized to the rdclk andwrclk clocks respectively. The prefixes wr and rd represent the signals that aresynchronized by the wrclk and rdclk clocks and Output Ports DescriptionThis table lists the signals of the FIFO intel FPGA IP core.

8 The term series refers to all the device families of aparticular device. For example, Stratix series refers to the Stratix IV and Stratix V, unless (2)InputYesPositive-edge-triggered (3)InputYesPositive-edge-triggered to synchronize the following ports: data wrreq wrfull wrempty wrusedwrdclk (3)InputYesPositive-edge-triggered (2)Only applicable for the SCFIFO function.(3)Applicable for both of the DCFIFO intel FPGA IP User Guide683522 | FeedbackFIFO intel FPGA IP User Guide5 PortTypeRequiredDescriptionUse to synchronize the following ports: q rdreq rdfull rdempty rdusedwdata (4)InputYesHolds the data to be written in the FIFO intel FPGA IP core whenthe wrreq signal is asserted.

9 If you manually instantiate the FIFOI ntel FPGA IP core, ensure the port width is equal to thelpm_width (4)InputYesAssert this signal to request for a write that the following conditions are met: Do not assert the wrreq signal when the full (for SCFIFO) orwrfull (for DCFIFO) port is high. Enable the overflowprotection circuitry or set the overflow_checking parameterto ON so that the FIFO intel FPGA IP core can automaticallydisable the wrreq signal when it is full. The wrreq signal must meet the functional timing requirementbased on the full or wrfull signal. Do not assert the wrreq signal during the deassertion of theaclr signal. Violating this requirement creates a race conditionbetween the falling edge of the aclr signal and the rising edgeof the write clock if the wrreq port is set to high.

10 For both theDCFIFO functions that target Stratix series and Cyclone series, you have the option to automatically add a circuit tosynchronize the aclr signal with the wrclk clock, or set thewrite_aclr_synch parameter to ON. Use this option toensure that the restriction is (4)InputYesAssert this signal to request for a read operation. The rdreqsignal acts differently in normal mode and show-ahead that the following conditions are met: Do not assert the rdreq signal when the empty (for SCFIFO)or rdempty (for DCFIFO) port is high. Enable the underflowprotection circuitry or set the underflow_checkingparameter to ON so that the FIFO intel FPGA IP core canautomatically disable the rdreq signal when it is empty.