High Bandwidth Memory (HBM2) Interface Intel® FPGA …

1 high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP User GuideUpdated for intel Quartus Prime design Suite: Version: VersionSend FeedbackUG-20031ID: 683189 Version: About the high Bandwidth Memory ( hbm2 ) Interface intel FPGA Release Introduction to high Bandwidth hbm2 in intel Stratix 10 hbm2 DRAM intel Stratix 10 hbm2 intel Stratix 10 hbm2 Controller 73. intel Stratix 10 hbm2 intel Stratix 10 hbm2 intel Stratix 10 UIB intel Stratix 10 hbm2 Controller intel Stratix 10 hbm2 Controller Creating and Parameterizing the high Bandwidth Memory ( hbm2 ) Interface IntelFPGA Creating an intel Quartus Prime Pro Edition Project for high Bandwidth Memory ( hbm2 ) Interface FPGA Parameterizing the high Bandwidth Memory ( hbm2 ) Interface intel FPGA General Parameters for high Bandwidth Memory ( hbm2 ) Interface IntelFPGA FPGA I/O Parameters for high Bandwidth Memory ( hbm2 )

2 Interface IntelFPGA Controller Parameters for high Bandwidth Memory ( hbm2 ) Interface IntelFPGA Diagnostic Parameters for high Bandwidth Memory ( hbm2 ) Interface IntelFPGA Example Designs Parameters for high Bandwidth Memory ( hbm2 ) Interface intel FPGA Register Map IP-XACT Support for hbm2 Pin Planning for the high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP ..325. Simulating the high Bandwidth Memory ( hbm2 ) Interface intel FPGA high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP Example Simulating high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP withModelSim* and Questa*.

3 Simulating high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP with SynopsysVCS*.. Simulating high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP with Riviera-PRO*.. Simulating high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP with CadenceXcelium* Parallel Simulating high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP for Simulating high Bandwidth Memory ( hbm2 ) Interface IP Instantiated in Your high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP high Level Block high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP Controller Interface Bandwidth Memory ( hbm2 )

4 Interface intel FPGA IP User GuideSend Clock Reset Calibration Status Memory Interface User- Interface AXI User- Interface Sideband APB Avalon Memory -Mapped (AVMM) Interface User AXI Interface AXI Write AXI Read Improving User Logic to hbm2 Controller AXI Interface User APB Interface Advanced Peripheral Bus APB Interface User-controlled Accesses to the hbm2 User-controlled Temperature and Calibration Status Controller Idle State Status .. Power Down ECC Error User ECC Error Correction and Soft AXI AXI Switch Selection in hbm2 IP Catalog high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP Controller high Bandwidth Memory ( hbm2 ) DRAM high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP hbm2 IP high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP DRAM Temperature high Bandwidth Memory ( hbm2 ) Interface intel FPGA IP User Guide Document Revision History for high Bandwidth Memory ( hbm2 )

5 Interface IntelFPGA IP User 89 ContentsSend FeedbackHigh Bandwidth Memory ( hbm2 ) Interface intel FPGA IP User Guide31. About the high Bandwidth Memory ( hbm2 ) InterfaceIntel FPGA Release InformationIP versions are the same as the intel Quartus Prime design Suite software versionsup to From intel Quartus Prime design Suite software version or later, IPcores have a new IP versioning IP versioning scheme ( ) number changes from one software version toanother. A change in: X indicates a major revision of the IP. If you update your intel Quartus Primesoftware, you must regenerate the IP.

6 Y indicates the IP includes new features. Regenerate your IP to include these newfeatures. Z indicates the IP includes minor changes. Regenerate your IP to include Bandwidth Memory ( hbm2 ) Interface intel FPGA IP Core CurrentRelease InformationItemDescriptionIP Quartus Prime | FeedbackIntel Corporation. All rights reserved. intel , the intel logo, and other intel marks are trademarks of IntelCorporation or its subsidiaries. intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with intel 's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice.

7 intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by intel . intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 Registered2. Introduction to high Bandwidth MemoryHigh Bandwidth Memory (HBM) is a JEDEC specification (JESD-235) for a wide, highbandwidth Memory device. The next generation of high Bandwidth Memory , hbm2 , isdefined in JEDEC specification JESD-235A.

8 The hbm2 implementation in intel Stratix 10 devices complies with high Bandwidth Memory DRAM is tightly coupled to the host die with a distributedinterface. The Interface is divided into independent channels, each completelyindependent of one another. Each channel Interface maintains a 128-bit data bus,operating at DDR data hbm2 in intel Stratix 10 DevicesIntel Stratix 10 devices incorporate a high -performance FPGA fabric along with aHBM2 DRAM in a single package. intel Stratix 10 devices support up to a maximum oftwo hbm2 Stratix 10 devices incorporate intel s Embedded Multi-Die Interconnect Bridge(EMIB) technology to implement a silicon bridge between hbm2 DRAM Memory andthe Universal Interface Block Subsystem (UIBSS), which contains the hbm2 controller(HBMC), physical-layer Interface (PHY)

9 , and I/O ports to Interface to the hbm2 illustrated below, each intel Stratix 10 device contains a single universal interfacebus per hbm2 Interface , supporting 8 independent user Interface to the hbm2 controller is maintained through the AXI4 AXI interfaces are available in the user Interface from each hbm2 controller,with one AXI Interface available per hbm2 Pseudo Channel. hbm2 DRAM density of4GB and 8GB are Stratix 10 Device with UIB, EMIB, and hbm2 DRAM683189 | FeedbackIntel Corporation. All rights reserved. intel , the intel logo, and other intel marks are trademarks of IntelCorporation or its subsidiaries.

10 intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with intel 's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by intel . intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.