High-Speed Serial I/O Made Simple - Xilinx

1 Connectivity Solutions Connectivity Solutions Edition High-Speed Serial I/O made Simple A Designers' Guide, with FPGA Applications High-Speed Serial I/0 made Simple A Designers Guide, with FPGA Applications High-Speed Serial I/O. How Do You Get 10-Gbps I/O Performance? High-Speed Serial I/O can be used to solve system interconnect design challenges. made Simple A Designers' Guide, with FPGA Applications Such I/Os, when integrated into a highly programmable digital environment such as an FPGA, allow you to create high -performance designs that were never possible before. This book discusses the many aspects of High-Speed Serial designs with real world examples of how to implement working designs, including: Basic I/O Concepts Differential signaling, System Synchronous, and Source Synchronous design techniques. Pros and Cons of different implemenations How to evaluate the cost advantages, the reduced EMI, the maximum data flow, and so on.

2 SERDES Design Basic theory, how to implement highly efficient Serial to parallel channels, coding schemes, and so on. Design Considerations Standard and custom protocols, signal integrity, impedance, shielding, and so on. Testing Interpreting eye patterns, reducing jitter, interoperability considerations, bit error testers, and so on. Edition Xcell Publications help you solve design challenges, bringing you the awareness of the latest tools, devices, and technologies;. knowledge on how to design most effectively; and the next steps for implementing working solutions. See all of our books, magazines, technical journals, solutions guides, and brochures at: by Abhijit Athavale R. Edition April, 2005 PN 0402399 and Carl Christensen CONNECTIVITY SOLUTIONS: EDITION PRELIMINARY INFORMATION. High-Speed Serial I/O. made Simple A Designer's Guide with FPGA Applications by Abhijit Athavale Marketing Manager, Connectivity Solutions, Xilinx , Inc.

3 And Carl Christensen Technical Marketing High-Speed Serial I/O made Simple . 2005 Xilinx , Inc. All rights reserved. Xilinx , the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx , Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information stated in this book is Preliminary Information and is not to be used for design purposes. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

4 All terms mentioned in this book are known to be trademarks or service marks and are the property of their respective owners. Use of a term in this book should not be regarded as affecting the validity of any trademark or service mark. All rights reserved. No part of this book may be reproduced, in any form or by any means, without written per- mission from the publisher. For copies of this book, write to: Xilinx Connectivity Solutions Product Solutions Marketing/ Xilinx Worldwide Marketing Dept. 2450, 2100 Logic Drive, San Jose, CA 95124. Tel: , Fax: Preliminary Edition April 2005. PN0402399. ii Acknowledgements We would like to offer our deepest thanks to Paul Galloway and Craig Abramson. Without their constant motivation, direction, and encouragement, we could not have completed this project. We are also indebted to Ryan Carlson for his invaluable assistance in structuring the book, and to Chuck Berry for his great support and sales interface.

5 To a host of reviewers that included Matt DiPaolo, Mike Degerstrom, and Scott Davidson, we want to offer our gratitude. They kept us honest, accurate, and up to date. To Babak Hedayati and Tim Erjavec for their unwavering support and encouragement Finally, we offer special thanks to Ray Johnson. He fully supported our effort and placed his personal stamp of approval on this book by providing the Forward. PRELIMINARY INFORMATION iii High-Speed Serial I/O made Simple . iv TABLE OF CONTENTS. Acknowledgements .. iii Foreword About the Authors .. vii Introduction I/O Performance Limitations ..1. Digital Design Solutions for I/O ..1. Introducing Multi-Gigabit Serial ..1. History of Digital Electronic Communication ..2. Basic I/O Concepts ..3. Differential Signal ..4. System-Synchronous, Source-Synchronous, and Self-Synchronous ..5. Parallel Transfers.

6 10. Constant I/O Improvement ..10. Why Do We Need Gigabit Serial I/O? Design Concerns ..11. Gigabit Serial I/O Advantages..11. Maximum Data Flow ..11. Pin Count ..14. Simultaneous Switching Outputs ..15. EMI ..15. Cost ..15. Predefined Protocols ..16. What are the Disadvantages?..16. Where Will Gigabit I/O Be Used? ..16. Chip-to-Chip ..16. Board-to-Board/Backplanes ..17. Box-to-Box ..18. The Future of Multi-gigabit Designs..18. Technology Real-World Serial I/O ..19. Gigabit- Serial Implementations ..19. SERDES ..20. History of SERDES and CDR ..20. Basic Theory of Operations and Generic Block Diagram ..21. Why Are They So Fast? ..23. Line Encoding Schemes ..25. PRELIMINARY INFORMATION Xilinx v High-Speed Serial I/O made Simple . 8b/10b Encoding/Decoding .. 26. Running Disparity .. 26. Control Characters .. 27. Comma Detection.. 27. Scrambling .. 29.

7 4b/5b 64b/66b .. 31. 4b/5b 64b/66b Trade-Offs .. 34. Introduction to Packets .. 35. Reference Clocking Requirements .. 36. Clock Correction .. 37. Receive and Transmit Buffers.. 38. Channel Bonding .. 39. Physical Signaling .. 40. Pre-Emphasis .. 42. Differential Transmission Lines .. 45. Line Equalization .. 47. Optical.. 51. Bit Error Rate .. 52. Realities of Testing .. 53. CRC .. 53. FEC Used in Some Applications .. 54. SERDES Technology Facilitates I/O Design.. 55. Designing with Gigabit Serial I/O. The Challenges of Multi-Gigabit Transceiver Design.. 57. Design Considerations and Choices You Can Use .. 57. Protocols .. 57. Standard Protocols .. 58. Custom Protocols .. 62. Signal Integrity .. 65. Impedance .. 65. Power.. 66. Shielding .. 73. Boards, Connectors, and Cables .. 73. Printed Circuit Board Design .. 73. Connector Selection .. 79. Cable Selection.

8 81. Simulation .. 83. Analog .. 83. Digital .. 84. vi Xilinx TABLE OF CONTENTS. Test and Measurement ..86. Sampling Oscilloscopes and Digital Communication Analyzers ..86. Time Delay Reflectometer ..87. Eye Patterns..89. Jitter ..93. Generators and Bit Error Testers ..94. Putting the Equipment to Use ..96. Multi-gigabit Debug Hints ..97. Interoperability ..99. Protocol Level ..99. Electrical..100. Other Resources ..100. Design Services ..100. Testing Centers ..100. Development Platforms ..101. Xilinx Your Design Partner Serial I/O Design Considerations ..103. One Stop Serial I/O Web Portal ..103. Signal Integrity Central..105. Additional References ..106. Xilinx A Powerful Design Partner ..107. World-Class Xilinx Support ..108. Sample SERDES Data -- RocketIO X Transceiver Overview Basic Architecture and Capabilities ..109. RocketIO X Transceiver Instantiations.

9 112. HDL Code Examples ..112. Available Ports ..113. Primitive Attributes ..120. Modifiable Attributes ..126. Byte Mapping ..126. Digital Design Considerations..127. Top-Level Architecture ..128. Transmit Architecture ..128. Receive Architecture ..129. Operation Modes ..129. Block Level Functions ..130. Classification of Signals and Overloading ..130. PRELIMINARY INFORMATION Xilinx vii High-Speed Serial I/O made Simple . Bus Interface.. 132. 8b/10b .. 133. Vitesse Disparity Example .. 139. Comma Detection.. 140. 64b/66b .. 144. Functions Common to All Protocols .. 150. Channel Bonding .. 152. Status and Event Bus .. 155. 8b/10b Tables Valid Data and Control Characters .. 161. A Comparison of Two Different FPGA-to-FPGA Data Links Abstract .. 173. Introduction.. 173. Requirements and System Architecture Concerns/Features .. 174. The Slow Link .. 174.

10 The Fast Link .. 174. Implementation Details .. 177. The Slow Link .. 177. The Fast Link .. 177. Proving Our Concept .. 178. Testing the Slow Link.. 178. Testing the Fast Link .. 182. Conclusion .. 186. Acknowledgements .. 186. Glossary viii Xilinx Foreword An invasion of armies can be resisted, but not an idea whose time has come.. - Victor Hugo (1802 1885) 'Histoire d'un crime,' 1852. There are only a handful of occasions in life when we are fortunate enough to be part of a new dis- covery or an idea whose time has finally come. Some of these ideas or innovations can drastically change the universe we live in. Think of how it must have felt to be in the National Institutes of Health lab when bio-scientists put the finishing touches on mapping the entire human genome . identifying the last gene in our DNA structure. Or at Bell Labs when Bardeen, Brattain, and Shockley demonstrated the first working transistor that led to a communications revolution.