使い始めユーザーガイド - Intel

1 Intel Quartus Prime Pro EditionUser GuideGetting StartedUpdated for Intel Quartus Prime Design Suite: VersionSend FeedbackUG-20129ID: 683463 Version: Introduction to Intel Quartus Prime Pro Selecting an Intel Quartus Prime Software Introduction to Intel Quartus Prime Pro Edition Revision Managing Intel Quartus Prime Viewing Basic Project Using the Compilation Viewing Project Viewing Project Automated Problem Intel Quartus Prime Project Project File Best Managing Project Specifying the Target Device or Optimizing Project Managing Logic Design Including Design Creating a Project Managing Timing Integrating Other EDA Exporting Compilation Exporting a

2 Version-Compatible Compilation Database .. Importing a Version-Compatible Compilation Database .. Creating a Design Exporting a Design Reusing a Design Viewing Quartus Database File Clearing Compilation Migrating Projects Across Operating Migrating Design Files and Design Library Migration Archiving Manually Adding Files To Archiving Projects for Service Archiving Projects for External Revision Creating Database-Only Command-Line Project Revision Project Archive Project Database Managing Projects Revision Design Design Create a Design Specification and Test Plan for the Target Device Migration Plan for

3 Intellectual Property 51 ContentsIntel Quartus Prime Pro Edition User Guide: Getting StartedSend Plan for Standard Plan for Device Plan for Device Power Plan for Interface I/O Simultaneous Switching Noise Plan for other EDA Third-Party Synthesis Third-Party Simulation Plan for On-Chip Debugging Plan HDL Coding Design Recommended HDL Coding Managing Plan for Hierarchical and Team-Based Flat Compilation without Design Design Planning Revision Introduction to Intel FPGA IP IP Catalog and Parameter The Parameter Installing and Licensing Intel FPGA IP Intel FPGA IP Evaluation IP General

4 Adding IP to IP Best Practices for Intel FPGA Specifying the IP Core Parameters and Options ( Intel Quartus Prime Pro Edition).. IP Core Generation Output ( Intel Quartus Prime Pro Edition).. Scripting IP Core Modifying an IP Upgrading IP Upgrading IP Cores at Migrating IP Cores to a Different Troubleshooting IP or Platform Designer System Simulating Intel FPGA IP Generating IP Simulation Scripting IP Simulating Platform Designer Synthesizing IP Cores in Other EDA Instantiating IP Cores in Example Top-Level Verilog HDL Example Top-Level VHDL Support for the IEEE 1735 Encryption Introduction to Intel FPGA IP Cores Revision 1005.

5 Migrating to Intel Quartus Prime Pro Keep Pro Edition Project Files Upgrade Project Assignments and Modify Entity Name Resolve Timing Constraint Entity Verify Generated Node Name Replace Logic Lock (Standard) 104 ContentsSend FeedbackIntel Quartus Prime Pro Edition User Guide: Getting Modify Signal Tap Logic Analyzer Remove References to .qip Remove Unsupported Feature Upgrade IP Cores and Platform Designer Upgrade Non-Compliant Design Verify Verilog Compilation Unit .. Update Entity Ensure Distinct VHDL Namespace for Each Remove Unsupported Parameter Remove Unsized Constant from WYSIWYG Remove Non-Standard Declare Objects Before Initial Confine systemverilog Features to systemverilog Avoid Assignment Mixing in Always Avoid Unconnected, Non-Existent Avoid Illegal Parameter Update Verilog HDL and VHDL Type Migrating to Intel Quartus Prime Pro Edition Revision 114A.

6 Intel Quartus Prime Pro Edition User 1157. Document Quartus Prime Pro Edition User Guide: Getting StartedSend Feedback41. Introduction to Intel Quartus Prime Pro EditionThis user guide describes basic concepts and operation of the Intel Quartus PrimePro Edition design software, including GUI and project structure basics, initial designplanning, use of Intel FPGA IP, and migration to Intel Quartus Prime Pro Edition. Thissoftware provides a complete design environment for the most advanced IntelAgilex , Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX FPGA and Intel Quartus Prime software GUI supports easy design entry, fast designprocessing, straightforward device programming, and integration with other industry-standard EDA tools.

7 The user interface makes it easy for you to focus on your design not on the design tool. The modular Compiler streamlines the FPGA developmentprocess, and ensures the highest performance for the least Quartus Prime Pro Edition Software GUI683463 | FeedbackIntel Corporation. All rights reserved. Intel , the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel 's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice.

8 Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel . Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 RegisteredThe Intel Quartus Prime Pro Edition software expands on the capabilities of the IntelQuartus Prime Standard Edition, and provides unique features that support the latestIntel FPGAs.

9 Select the Intel Quartus Prime software edition that provides the devicesupport and features you require, as Selecting an Intel Quartus Prime Software Editionon page 6 Intel Quartus Prime Pro Edition software offers flexible design methodologies,advanced synthesis, and supports the latest Intel FPGA architectures and hierarchicaldesign flows. The Compiler provides powerful and customizable design processing toachieve the best possible design implementation in silicon. The following features areunique to the Intel Quartus Prime Pro Edition: Hyper-Aware Design Flow use Hyper-Retiming and Fast Forward compilation toreach the highest performance in Intel Agilex and Intel Stratix 10 devices.

10 Intel Quartus Prime Pro Edition synthesis integrates new, stricter language parsersupporting all major IEEE RTL languages, with enhanced algorithms, and parallelsynthesis capabilities. Added support for systemverilog 2009. Hierarchical project structure preserve individual post-synthesis, post-placement,and post-place and route results for each design instance. Allows optimizationwithout impacting other partition placement or routing. Incremental Fitter Optimizations run and optimize Fitter stages Fitter stage generates detailed reports. Faster, more accurate I/O placement plan interface I/O in Interface Planner.