MAX 10 の汎用 I/O のユーザーガイド - Intel

1 MAX 10 I/O quartus prime Design Suite Innovation DriveSan Jose, CA MAX 10 I/O .. 1-1 MAX 10 I/O .. 1-2 MAX 10 I/O .. 1-3 MAX 10 I/O .. 2-1 MAX 10 I/O .. 2-1 MAX 10 I/O .. 2-5 MAX 10 I/O ..2-9 MAX 10 I/O ..2-10 MAX 10 I/O ..2-11 MAX 10 I/O .. 2-14 .. 2-14 I/O .. 2-14I/O .. 2-22 I/O .. 2-22 I/O .. 2-23 MAX 10 I/O .. 2-25 MAX 10 I/O .. 3-1 VCCIO ..3-1 : I/O .. 3-2 LVTTL / LVCMOS .. 3-3 : LVDS I/O .. 3-4 I/O .. 3-4 - I/O .. 3-5 : I/O .. 3-9 ..3-10 MAX 10 E144 .. 3-11 MAX 10 I/O .. 4-1 GPIO IP .. 4-1 GPIO IP ..4-2 .. 4-5 GPIO IP ..5-1 -2 Altera Corporation GPIO.

2 5-1 GPIO .. 5-5 MAX 10 I/O .. A-1 MAX 10 I/O .. B-1 -3 Altera CorporationMAX 10 I/O MAX 10 I/O GPIO I/O IOE GPIO IP IOE I/O I/O I/O GPIO IP I/O DDIO I/O GPIO 2-1 MAX 10 I/O MAX 10 I/O 3-1 MAX 10 I/O MAX 10 I/O 4-1 MAX 10 I/O MAX 10 I/O 5-1 GPIO IP MAX 10 GPIO IP 6-1 MAX 10 I/O Altera GPIO Lite IP Intel Corporation. All rights reserved. Intel , the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, quartus and Stratix words and logos are trademarks ofIntel Corporation or its subsidiaries in the and/or other countries.

3 Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel 's standard warranty, but reserves the right to make changes to any products and services at any time without assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Intel . Intel customers are advised to obtain the latest version of device specifications before relying on any published informationand before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 Innovation Drive, San Jose, CA 95134 MAX 10 I/O 1-1: MAX 10 M153153 MBGAU169169 UBGAE144144 EQFP 8 mm 8 mm11 mm 11 mm22 mm 22 mm mm10M0211213010110M0411213010110M0811213 010110M16 13010110M25 10110M40 10110M50 101 1-2: MAX 10 V3636 WLCSPV8181 WLCSPU324324 UBGAF256256 FBGAF484484 FBGAF672672 FBGA 3 mm 3mm4 mm 4mm15 mm 15mm17 mm 17mm23 mm 23mm27 mm 27 mm mm10M0227 160 10M04 246178 10M08 56246178250 10M16 246178320 10M25 178360 10M40 17836050010M50 1783605001-2 MAX 10 I/O CorporationMAX 10 I/O MAX 10 I/O 1-1.

4 MAX 10 I/O I/O I/O I/O DevicePackageV36V81M153U169U324F256E144F 484F67210M0210M0410M0810M1610M2510M4010M 50 : quartus prime PinPlanner Pin Migration View 4-5 10 I/O 1-3 MAX 10 I/O Altera Corporation MAX 10 I/O MAX 10 I/O I/O MAX 10 I/O I/O I/O I/O 1-1 MAX 10 I/O MAX 10 I/O MAX 10 I/O I/O 2-1: MAX 10 I/O I/O I/O 10M02 V36 I/O 10M08 V81 I/O 10M50 E144 1A 1BI/O / V LVTTL V LVCMOS V VLVCMOS V LVCMOS V LVCMOS JESD8-7 Intel Corporation.

5 All rights reserved. Intel , the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, quartus and Stratix words and logos are trademarks ofIntel Corporation or its subsidiaries in the and/or other countries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel 's standard warranty, but reserves the right to make changes to any products and services at any time without assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Intel . Intel customers are advised to obtain the latest version of device specifications before relying on any published informationand before placing orders for products or services.*Other names and brands may be claimed as the property of :2015 Innovation Drive, San Jose, CA 95134I/O / V LVCMOS V LVCMOS V PCI PCI Rev.

6 V V V V SSTL-2 Class I DDR1 JESD8-9 BSSTL-2 Class II DDR1 JESD8-9 BSSTL-18 Class I DDR2 JESD8-15 SSTL-18 Class II DDR2 JESD8-15 SSTL-15 Class I DDR3 SSTL-15 Class II DDR3 SSTL-15 (1) DDR3 JESD79-3 DSSTL-135(1) DDR3L V HSTL Class I DDR II+ QDR II+ RLDRAM 2 JESD8-6(1)MAX 10 16 25 40 50 2-2 MAX 10 I/O CorporationMAX 10 I/O I/O / V HSTL Class II DDR II+ QDR II+ RLDRAM V HSTL Class I DDR II+ QDR II+ QDR II RLDRAM V HSTL Class II DDR II+ QDR II+ QDR II RLDRAM V HSTL Class I V HSTL Class II JESD8-16 AHSUL-12(1) LPDDR2 SSTL-2 Class I Class II (2) (3)DDR1 JESD8-9B SSTL-18 ClassI Class II (2) (3)DDR2 JESD8-15 SSTL-15 ClassI Class II (2) (3)DDR3 SSTL-15 (2) (3)DDR3 JESD79-3D SSTL-135 (2) (3)DDR3L V HSTLC lass I Class II (2) (3)DDR II+ QDR II+ RLDRAM 2 JESD8-6 V HSTLC lass I Class II (2) (3)DDR II+ QDR II+ QDR II RLDRAM 2 JESD8-6(2) 2 1 (3) 2 2 10 I/O 2-3 MAX 10 I/O Altera Corporation I/O / V HSTLC lass I Class II (2) (3) JESD8-16A HSUL-12 (2) (3)LPDDR2 LVDS (4) ANSI/TIA/EIA-644 LVDS ANSI/TIA/EIA-644 Mini-LVDS (4) Mini-LVDS RSDS (4) RSDS 1R RSDS 3R PPDS (4)

7 PPDS LVPECL Bus LVDS (5) (4) LVDS I/O LVDS I/O (5) 2 2 2-4 MAX 10 I/O CorporationMAX 10 I/O I/O / TMDS Sub-LVDS (6) SLVS (7) HiSpi 2-14 MAX 10 I/O I/O I/O LVDS Transmitter I/O Termination Schemes, MAX 10 High-Speed LVDS I/O User GuideMAX 10 I/O 2-2: MAX 10 I/O : I/O I/O I/O I/O LVDS I/O I/O PLL_CLKOUT LVDS I/O I/O (6) (7) 2 10 I/O 2-5 MAX 10 I/O Altera Corporation I/O VCCIO V VREF V PLL_CLKOUTMEM_CLKCLKDQS V V V V V V V V V V (8) V (8) V (8) V (8) SSTL-2 Class SSTL-2 Class SSTL-18 Class SSTL-18 Class SSTL-15 Class SSTL-15 Class V HSTL V HSTL V HSTL (8)

8 LVTTL 2-6 MAX 10 I/O CorporationMAX 10 I/O I/O VCCIO V VREF V PLL_CLKOUTMEM_CLKCLKDQS V HSTL V HSTL V HSTL SSTL-2 ClassI Class II SSTL-18 Class I Class II SSTL-15 Class I Class II SSTL-15 SSTL-135 V HSTLC lass I Class II V HSTLC lass I Class II V HSTLC lass I Class II HSUL-12 LVDS LVDS 10 I/O 2-7 MAX 10 I/O Altera Corporation I/O VCCIO V VREF V PLL_CLKOUTMEM_CLKCLKDQS I/OMini-LVDS Mini-LVDS RSDS RSDS 1R RSDS 3R PPDS PPDS Bus MAX 10 Device Pin-Out Files 2-1 MAX 10 I/O 2-11 MAX 10 I/O MAX 10 LVDS SERDES I/O Standards Support MAX 10 High-Speed LVDS I/O Location2-8 MAX 10 I/O CorporationMAX 10 I/O MAX 10 I/O MAX 10 I/O IOE I/O 1 5 SDR Single Data Rate DDR Double Data Rate I/O I/O 4 I/O MAX 10 VREF RUP RDN CLKPIN PLLCLKOUT I/O I/O IOE 1 2 OE 2 2 2 OE DDR - OE - IOE I/O I/O 10 I/O 2-9 MAX 10 I/O Altera Corporation 2-1.

9 IOE DQENADQENAVCCIOVCCIOO ptional PCI ClampProgrammablePull-UpResistorBus HoldInput Pin toInput Register Delayor Input Pin to Logic Array DelayOutputPin Delayclkinoe_indata_in0data_in1sclr/pres etChip-Wide Resetaclr/prnoe_outclkoutOEOE RegisterCurrent Strength ControlOpen-Drain OutColumnor RowInterconnectio_clk[ ]Slew Rate ControlACLR/PRNACLR/PRNO utput RegisterDQENAACLR/PRNI nput Register MAX 10 Power Management User Guide I/O MAX 10 I/O I/O I/O 4 DDR3 I/O I/O DDR3 I/O I/O I/O DDR3 I/O I/O I/O 2-10 MAX 10 I/O CorporationMAX 10 I/O I/O MAX 10 Device Pin-Out FilesMAX 10 I/O I/O I/O 2-2: MAX 10 02 I/O 125638 VREF1 VCCIO8 VREF8 VCCIO1 VCCIO5 VCCIO2 VCCIO3 VREF3 VCCIO6 VREF6 VREF2 VREF5 Low Speed I/OHigh Speed 10 I/O 2-11 MAX 10 I/O Altera Corporation 2-3.

10 MAX 10 04 08 I/O 1A1B2563487 VCCIO5 VCCIO2 VCCIO3 VREF3 VREF4 VCCIO4 VCCIO7 VCCIO8 VCCIO1 BVCCIO1 AVCCIO6 VREF6 VREF1 VREF2 VREF8 VREF7 VREF5 Low Speed I/OHigh Speed I/O2-12 MAX 10 I/O CorporationMAX 10 I/O 2-4: MAX 10 16 25 40 50 I/O 1A1B2563487 VCCIO5 VCCIO2 VCCIO3 VREF3 VREF4 VCCIO4 VCCIO7 VCCIO8 VCCIO1 BVCCIO1 AVCCIO6 VREF6 VREF1 VREF2 VREF8 VREF7 VREF5 Low Speed I/OHigh Speed I/OHigh Speed DDR3 I/OOCT MAX 10 Device Pin-Out Files High-Speed I/O Specifications I/O I/O 10 I/O 2-13 MAX 10 I/O Altera Corporation MAX 10 I/O MAX 10 I/O GPIO LVDS I/O DDR I/O 2-3: MAX 10 GPIO LVDS I/O DDR I/O I/O I/O LVDS I/O LVDS LVDS LVDS I/O I/O LVDS DDR I/O LVDS LVDS DDR DDR I/O DDR3 DDR3 MAX 10 16 25 40 50 2-1 MAX 10 I/O LVDS Transmitter I/O Termination Schemes, MAX 10 High-Speed LVDS I/O User Guide MAX 10 I/O VIL VIH LVTTL I/O MAX 10 Device Datasheet I/O MAX 10 I/O I/O 2-14 MAX 10 I/O CorporationMAX 10 I/O 2-4.