Intel Family Platform Controller Hub (PCH)

1 Order Number: 326776-003 Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)Datasheet June 20122 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH Intel PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN Intel 'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, Intel ASSUMES NO LIABILITY WHATSOEVER AND Intel DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF Intel PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE Intel 'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD Intel AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT Intel OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE Intel PRODUCT OR ANY OF ITS may make changes to specifications and product descriptions at any time, without notice.

2 Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on your local Intel sales office or your distributor to obtain the latest specifications and before placing your product of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: is a two-wire communications bus/protocol developed by Philips.

3 SMBus is a subset of the I2C bus/protocol and was developed by Intel . Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics and North American Philips computer system can provide absolute security under all conditions. Intel Trusted Execution Technology ( Intel TXT) requires a computer system with Intel Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). Intel TXT also requires the system to contain a TPM For more information, visit Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems.

4 Consult your PC manufacturer. For more information, visit Intel , and the Intel logo are trademarks of Intel Corporation in the and other countries.*Other names and brands may be claimed as the property of 2012, Intel This Manual .. Capability Overview .. 7 Series / C216 Chipset Family SKU Definition .. 542 Signal Media Interface (DMI) to Host Controller .. Express* .. Interface .. ATA Interface .. Interface .. Management SMBus System Management Real Time Clock Interface .. Miscellaneous Signals .. Intel High Definition Audio Link .. Controller Link .. Serial Peripheral Interface (SPI) .. Thermal Signals .. Testability Signals .. Clock Signals .. LVDS Signals .. Analog Display /VGA DAC Signals .. Intel Flexible Display Interface ( Intel FDI) .. Digital Display General Purpose I/O Signals.

5 Manageability Signals .. Power and Ground Signals .. Pin Straps .. External RTC Circuitry .. 973 PCH Pin Pull-Ups and Pull-Downs .. and I/O Signals Planes and Planes for Input Signals .. 1134 PCH and System Clocking Requirements .. Blocks .. Configuration Access Overview .. Related to Clock Configuration .. 1235 Functional Bridge (D30:F0) .. PCI Bus Interface .. PCI Bridge As an Initiator .. Memory Reads and I/O Reads and Writes .. Configuration Reads and Writes .. Locked Cycles .. Target / Master Secondary Master Latency Dual Address Cycle (DAC) .. Memory and I/O Decode to Parity Error Detection and Generation .. PCIRST# .. Peer Cycles .. PCI-to-PCI Bridge Model .. IDSEL to Device Number Mapping .. Standard PCI Bus Configuration PCI Legacy Mode .. Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7).

6 Interrupt Generation .. Power S3/S4/S5 Support .. Resuming from Suspended State .. Device Initiated PM_PME Message .. SMI/SCI SERR# Generation .. Hot-Plug .. Presence Detection .. Message Generation .. Attention Button Detection .. SMI/SCI Ethernet Controller (B0:D25:F0) .. GbE PCI Express* Bus Transaction Data Alignment .. Configuration Request Retry Status .. Error Events and Error Reporting .. Data Parity Error .. Completion with Unsuccessful Completion Status .. Ethernet Interface .. 82579 LAN PHY Interface .. PCI Power Management .. Wake Up .. Configurable Function Level Reset Support (FLR).. FLR Bridge (with System and Management Functions) (D31:F0).. LPC Interface .. LPC Cycle Types .. Start Field Definition .. Cycle Type / Direction (CYCTYPE + DIR).

7 SYNC Time-Out .. SYNC Error Indication .. LFRAME# I/O Cycles .. Bus Master Cycles .. LPC Power Management .. Configuration and PCH Implications .. Operation (D31:F0) .. Channel Fixed Priority .. Rotating Priority .. Address Compatibility Mode .. Summary of DMA Transfer Sizes .. Address Shifting When Programmed for 16-Bit I/O Count by Words Autoinitialize .. Software Commands .. DMA .. Asserting DMA Requests .. Abandoning DMA General Flow of DMA Transfers .. Terminal Verify Mode .. DMA Request Deassertion .. SYNC Field / LDRQ# Rules .. Timers (D31:F0) .. Timer Programming .. Reading from the Interval Timer .. Simple Read .. Counter Latch Read Back Command .. Interrupt Controllers (PIC) (D31:F0) .. Interrupt Generating Acknowledging Interrupts.

8 Hardware/Software Interrupt Sequence .. Initialization Command Words (ICWx).. ICW1 .. ICW2 .. ICW3 .. ICW4 .. Operation Command Words (OCW).. Modes of Operation .. Fully Nested Special Fully-Nested Automatic Rotation Mode (Equal Priority Devices).. Specific Rotation Mode (Specific Priority).. Poll Edge and Level Triggered Mode .. End of Interrupt (EOI) Operations .. Normal End of Automatic End of Interrupt Mode .. Masking Interrupts .. Masking on an Individual Interrupt Special Mask Steering PCI Interrupts .. Programmable Interrupt Controller (APIC) (D31:F0) .. Interrupt Interrupt Mapping .. PCI/PCI Express* Message-Based Interrupts .. IOxAPIC Address Remapping .. External Interrupt Controller Support .. Serial Interrupt (D31:F0) .. Start Data Stop Frame.

9 Specific Interrupts Not Supported Using SERIRQ .. Data Frame Format .. Real Time Clock (D31:F0).. Update Interrupts .. Lockable RAM Ranges .. Century Rollover .. Clearing Battery-Backed RTC RAM .. Processor Interface (D31:F0) .. Processor Interface Signals and VLW Messages .. INIT (Initialization) .. FERR# (Numeric Coprocessor Error).. NMI (Non-Maskable Interrupt) .. Processor Power Good (PROCPWRGD) .. Dual-Processor Usage Differences .. Virtual Legacy Wire (VLW) Power Management .. Features .. PCH and System Power States .. System Power SMI#/SCI Generation .. PCI Express* PCI Express* C-States .. Dynamic PCI Clock Control (Mobile Only).. Conditions for Checking the PCI Conditions for Maintaining the PCI Clock .. Conditions for Stopping the PCI Clock .. Conditions for Re-Starting the PCI Clock.

10 LPC Devices and CLKRUN# .. Sleep States .. Sleep State Initiating Sleep State .. Exiting Sleep PCI Express* WAKE# Signal and PME Event Message .. Sx-G3-Sx, Handling Power Deep Event Input Signals and Their Usage .. PWRBTN# (Power Button) .. RI# (Ring Indicator) .. PME# (PCI Power Management Event) .. SYS_RESET# Signal .. THRMTRIP# Signal .. ALT Access Mode .. Write Only Registers with Read Paths in ALT Access PIC Reserved Read Only Registers with Write Paths in ALT Access Power Supplies, Planes, and Plane Control with SLP_S3#, SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#.. # and Suspend-To-RAM Sequencing .. Signal .. # (Battery Low) (Mobile Only).. # Pin # and SRTCRST# .. #/GPIO30 Pin Behavior .. Power Management Theory of Operation .. Power Management (Desktop Only) .. APM Power Management (Mobile Only) .. Behavior.