Intel MAX 10 FPGA Device

1 Intel MAX 10 FPGA DeviceOverviewOnline VersionSend FeedbackM10-OVERVIEWID: 683658 Version: MAX 10 FPGA Device Advantages of Intel MAX 10 of Intel MAX 10 Device Features .. 4 Intel MAX 10 Device Ordering MAX 10 Device Feature MAX 10 Device Maximum Resources ..6 Intel MAX 10 Devices I/O Resources Per Package ..7 Intel MAX 10 Vertical Migration 7 Intel MAX 10 I/O Vertical Migration MAX 10 ADC Vertical Migration 8 Logic Elements and Logic Array Flash Multipliers and Digital Signal Processing Memory and General Purpose Memory 13 Document Revision History for Intel MAX 10 FPGA Device 13 ContentsIntel MAX 10 FPGA Device OverviewSend Feedback2 Intel MAX 10 FPGA Device OverviewIntel MAX 10 devices are single-chip, non-volatile low-cost programmable logicdevices (PLDs)

2 To integrate the optimal set of system highlights of the Intel MAX 10 devices include: Internally stored dual configuration flash User flash memory Instant on support Integrated analog-to-digital converters (ADCs) Single-chip Nios II soft core processor supportIntel MAX 10 devices are the ideal solution for system management, I/O expansion,communication control planes, industrial, automotive, and consumer InformationIntel MAX 10 FPGA Device DatasheetKey Advantages of Intel MAX 10 DevicesTable Advantages of Intel MAX 10 DevicesAdvantageSupporting FeatureSimple and fast configurationSecure on-die flash memory enables Device configuration in less than 10 msFlexibility and integration Single Device integrating PLD logic, RAM, flash memory.

3 Digital signalprocessing (DSP), ADC, phase-locked loop (PLL), and I/Os Small packages available from 3 mm 3 mmLow power Sleep mode significant standby power reduction and resumption in less than1 ms Longer battery life resumption from full power-off in less than 10 ms20-year-estimated life cycleBuilt on TSMC's 55 nm embedded flash process technologyHigh productivity design tools Intel Quartus Prime Lite edition (no cost license) Platform Designer (Standard) system integration tool DSP Builder for Intel FPGAs Nios II Embedded Design Suite (EDS)683658 | FeedbackIntel Corporation.

4 All rights reserved. Intel , the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel 's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel . Intel customers are advised to obtain the latest version of Device specifications before relyingon any published information and before placing orders for products or services.

5 *Other names and brands may be claimed as the property of :2015 RegisteredSummary of Intel MAX 10 Device FeaturesTable of Features for Intel MAX 10 DevicesFeatureDescriptionTechnology55 nm TSMC Embedded Flash (Flash + SRAM) process technologyPackaging Low cost, small form factor packages support multiple packagingtechnologies and pin pitches Multiple Device densities with compatible package footprints for seamlessmigration between different Device densities RoHS6-compliantCore architecture 4-input look-up table (LUT) and single register logic element (LE) LEs arranged in logic array block (LAB)

6 Embedded RAM and user flash memory Clocks and PLLs Embedded multiplier blocks General purpose I/OsInternal memory blocks M9K 9 kilobits (Kb) memory blocks Cascadable blocks to create RAM, dual port, and FIFO functionsUser flash memory (UFM) User accessible non-volatile storage High speed operating frequency Large memory size High data retention Multiple interface optionEmbedded multiplier blocks One 18 18 or two 9 9 multiplier modes Cascadable blocks enabling creation of filters, arithmetic functions, and imageprocessing pipelinesADC 12-bit successive approximation register (SAR) type Up to 17 analog inputs Cumulative speed up to 1 million samples per second ( MSPS)

7 Integrated temperature sensing capabilityClock networks Global clocks support High speed frequency in clock networkInternal oscillatorBuilt-in internal ring oscillatorPLLs Analog-based Low jitter High precision clock synthesis Clock delay compensation Zero delay buffering Multiple output tapsGeneral-purpose I/Os (GPIOs) Multiple I/O standards support On-chip termination (OCT) Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitterExternal memory interface (EMIF) (1)Supports up to 600 Mbps external memory (1)EMIF is only supported in selected Intel MAX 10 Device density and package to the External Memory Interface User Guide for more MAX 10 FPGA Device Overview683658 | MAX 10 FPGA Device OverviewSend Feedback4 FeatureDescription DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40, and 10M50.)

8 SRAM (Hardware support only)Note: For 600 Mbps performance, 6 Device speed grade is varies according to Device grade (commercial, industrial, orautomotive) and Device speed grade ( 6 or 7). Refer to the Intel MAX10 FPGA Device Datasheet or External Memory Interface Spec Estimatorfor more Internal configuration JTAG Advanced Encryption Standard (AES) 128-bit encryption and compressionoptions Flash memory data retention of 20 years at 85 CFlexible power supply schemes Single- and dual-supply Device options Dynamically controlled input buffer power down Sleep mode for dynamic power reductionIntel MAX 10 Device Ordering InformationFigure Ordering Code and Available Options for Intel MAX 10 DevicesV, Y.

9 Wafer-Level Chip Scale (WLCSP)E : Plastic Enhanced Quad Flat Pack (EQFP)M : Micro FineLine BGA (MBGA)U : Ultra FineLine BGA (UBGA)F : FineLine BGA (FBGA)Family SignaturePackage TypeWLCSP Package Type36 : 36 pins, 3 mm x 3 mm81 : 81 pins, 4 mm x 4 mmEQFP Package Type144 : 144 pins, 22 mm x 22 mmUBGA Package Type169 : 169 pins, 11 mm x 11 mm324 : 324 pins, 15 mm x 15 mmFBGA Package Type256 : 256 pins, 17 mm x 17 mm484 : 484 pins, 23 mm x 23 mm672 : 672 pins, 27 mm x 27 mmMBGA Package Type153 : 153 pins, 8 mm x 8 mmPackage Code180 : 180 pins, 6 mm x 5 mmOperating TemperatureFPGA Fabric Speed GradeOptional SuffixIndicates specific Device options or shipment method 6 (fastest)7810M16 DAU484I7G Feature Options02 : 2K logic elements04 : 4K logic elements08 : 8K logic elements16 : 16K logic elements25 : 25K logic elements40 : 40K logic elements50 : 50K logic elementsMember Code10M : Intel MAX 10 G : RoHS6ES : Engineering sample P : Leaded packageC : Commercial (T = 0 C to 85 C)I : Industrial (T = - 40 C to 100 C)A : Automotive (T = - 40 C to 125 C)JJJNote.

10 (1) DD OPN available only on 10M40 and 10M50 devices with F256, F484, and F762 : Single supply - compact featuresSA : Single supply - analog and flash features with RSU optionSL : Single supply - flash features with RSU optionDC : Dual supply - compact featuresDF : Dual supply - flash features with RSU optionDA : Dual supply - analog and flash features with RSU optionDD : Dual supply - analog and flash features with RSU option and flash access control (1)Note: The A6 speed grade of the Intel MAX 10 FPGA devices is not available by default inthe Intel Quartus Prime software.