Introduction to Deep Submicron CMOS Device Technology ...

1 Slide 1 Loke, Wee & PfiesterAgilent TechnologiesIntroduction to deep Submicron cmos Device Technology & Its Impact on circuit DesignAlvin Loke, Tin Tin Wee & James R. PfiesterAgilent Technologies, Fort Collins, COIEEE Solid-State Circuits SocietyDecember 8, 2004 Slide 2 Loke, Wee & PfiesterAgilent TechnologiesOutline cmos Technology Trends MOSFET Basics deep Submicron FET Fabrication Sequence Enabling Technologies Second-Order Consequences Dealing with Process Variations in Manufacturing ConclusionsDisclaimer A proper introductionalone would take weeks, let alone a whole semester Need to omit lots of nitty-gritty yet important process details Hopefully, we ll still learn lots of cooldevice physics Slide 3 Loke, Wee & PfiesterAgilent TechnologiesSource: Thompson et al.

2 , Intel (2002)Where is cmos Technology Today? Scaling is still alive & well 130nm now standard fare 90nm already in volume manufacturing 65nm integration tough but not insurmountable Some key trends: Aggressive scaling of gate CD (critical dimension) Scaling driven by exclusively by digital circuit needsSource: Wu et al., TSMC (2002)90nm Technology59nm59nmSlide 4 Loke, Wee & PfiesterAgilent TechnologiesWhy Aggressive FET Scaling? The road to higher digital performance Cload reduce parasitics (largely dominated by interconnect now) DV reduce VDDor logic swing, need for core & I/O FET s IFET all about moving charge quickly Hiccups along the way Interconnect scaling much more difficult than anticipated, especially Cu/low-K reliability FET leakage doesn t go well with VDDscalingtdelay CloadDVIFETI dsat Cox(W/L) (VGS - VT)2 How to beef up IFET?

3 Tweak with , Cox, L & VT Technology upgrades not necessarily compatible with analog designStress-Induced VoidingGot redundant vias?Slide 5 Loke, Wee & PfiesterAgilent TechnologiesThe Most Basic MOS Concept VT VT= FET ON voltage, , gate voltage required to form inversion layer connecting source shorts out back-to-back pn-junctions with substrateVT= VFB+ 2fb+QdepCoxfb= lnNAnikBTqp-substrate ++++++++++++++++ Qdepdepletionchargen inversion layerpoly gaten+sourcen+drainsiliconsurface+++++++ ++++++++ flatband (offset) voltage due to oxide charge & work function difference oxide capacitance per unit area = eox/ toxbulk potentialdepletion charge per unit area = qNAxdep NA(xdep 1/ NA)Remember E= r/ e?

4 Slide 6 Loke, Wee & PfiesterAgilent TechnologiesMore MOS Fundamentals (Energy Band Diagram)Formation of Inversion LayerVT= gate voltage required to reverse doping of silicon surface, , move fsby 2fbonset of inversion(surface is undoped)fbfsM O Sfs= 0onset of strong inversion(VTcondition)fsfsfbfsVTM O Sfs= -fbinversionlayerVT= VFB+ 2fb+QdepCoxoffsetbulk dropoxide dropECEVE iflatband(no field in silicon)fbfsEFEF siliconsurfaceM O Sfs= fbfb= lnNAnikBTqSlide 7 Loke, Wee & PfiesterAgilent TechnologiesReintroducing (..drum ) the MOSFETVGS> VTVDS> 0 (net source-to-drain current flow)Carriers easily overcome source barrierSurface is strongly invertedVGS VTVDS= 0 (no net current flow)Source barrier is loweredSurface is invertedVGS= 0 VDS= 0 (no net current flow)Large source barrier(back-to-back diodes)electronelectroncurrentcurrentSou rce: Sze (1981)Slide 8 Loke, Wee & PfiesterAgilent TechnologiesLife s Never So PerfectIdealIDSVDSR ealityNow plunging deep into a lot of interesting second-order MOSFET = voltage-controlled current sourceSlide 9 Loke, Wee & PfiesterAgilent TechnologiesWarp Speed Ahead Short-Channel Effect (SCE) Prominent in older cmos technologies How to minimize SCE?

5 Minimize volume of charge depleted by source/drain junctions Higher substrate doping for thinner junction depletion regions (xdep 1/ N ) Higher VT& junction capacitance not consistent with scaling Shallower source/drain junctions Higher source/drain resistance smaller drive currents Tighter gate coupling to surface potential Thinner gate oxide of surface potential direct tunneling leakage Higher K gate dielectrics Other SCE problems: large electric fields carrier vsat& degradationVTDrawn Channel Length, LVTrolloff at shorter L since less charge must be depleted to achieve surface inversionjunctiondepletionregionpoly gaten+n+p-substratepoly gaten+n+p-substratedepleted bygate chargeSlide 10 Loke, Wee & PfiesterAgilent TechnologiesDeep Submicron FET Fabrication SequenceWell Implantation2n-wellp-wellGate Oxidation &Poly Definition3gate oxideSource/Drain Extension& Halo Implantation4halosSpacer Formation &Source/Drain Implantation5 Salicidation6silicidepFETnFETS hallow Trench Isolation1 STIoxidep-Si substrateSlide 11 Loke, Wee & PfiesterAgilent TechnologiesStep-and-Scan Projection Lithography Previous generations used G-line (436nm) & I-line (365nm)

6 Steppers (refractive 4X-projection optics) Technology trends More aggressive CD s shorter llll Higher NA lenses $$$ Larger reticle field sizes $$$ Step-and-scan enabled resolution & CD control for critical layersbeyond m node Slide reticle & wafer across narrow slit of light Aberration-free high-NA optics only required along 1-D but now requires high-precision constant-velocity stages Still much cheaper than optics optimized in 2-D Rectangular reticle size shorter edge limited by slit width Relatively weak intensity of deep -UV source required development of very sensitive chemically-amplifiedresists for throughputRayleigh s Equation: Resolution l/ NASource: NikonDeep-UV SlitSourceExcimer LaserKrF (248nm) or ArF (193nm)Slide 12 Loke, Wee & PfiesterAgilent TechnologiesMore Lithography Tricks Sharp features ( , corners) are lost because diffraction attenuates & distorts higher spatial frequencies (low-pass optical filtering) Compensate for diffraction effects for features much smaller than exposure l manage sub-lconstructive & destructive interference Software complexity during mask fabricationOptical Proximity Correction (OPC) Add scattering features to sharpen corners Used extensively for poly gate definitionPhase Shift Masking (PSM)

7 Modulate optical path through mask Used extensively for contacts & vias Complicated for irregular patternsNon-OptimizedOptimizedMaskResist PatternSource: Socha, ASML (2004)Source: Plummer, Stanford (2004)MaskAmplitudeOf MaskIntensityat WaferAmplitudeat Wafer180 phaseshiftSlide 13 Loke, Wee & PfiesterAgilent TechnologiesBasics of LOCOS Isolation m & Earlier Industry played lots of tricks to reduce width of bird s beak & make field oxide coplanar with active areas Required very careful understanding of visco-elastic properties of oxide during thermal oxidation LOCOS ran out of gas beyond thermal field oxide1 Deposit & pattern thin Si3N4oxidation maskStrip Si3N4oxidation mask3bird s beakDepth of Focus Resolution / NASlide 14 Loke, Wee & PfiesterAgilent TechnologiesShallow Trench Isolation (STI) m & Beyond 12345 Advantages over LOCOS technologies Reduced active-to-active spacing (no bird s beak)

8 Planar surface for gate lithographyDeposit & pattern thin Si3N4etch mask & polish stopEtch silicon around active area profile critical to minimize stressGrow liner SiO2, then deposit conformal SiO2 void-free deposition is criticalCMP excess SiO2 Strip Si3N4polish stopetched away in subsequent oxide cleansSlide 15 Loke, Wee & PfiesterAgilent TechnologiesLet s Think a Little Bit More About CMP Ideal world for CMP: want perfectperiodicity of patterns throughout wafer Need to throw in dummy features to minimize pattern density variations optimize planarity Polishing pad will flexoxide CMPdishingwafer carrierin situpad conditioner(critical)polishing tablepolishingpadwafer(facing down)slurryopticalendpointdetectionCMP Technology pioneered by IBM Leveraged expertise from lens polishingSlide 16 Loke, Wee & PfiesterAgilent TechnologiesAlways Think Dummies in Any CMP Process Dummification is key to minimize topography in any CMP process Add dummy patterns to open spaces to minimize layout density variations Added design complexity to check layout density & insert dummy patterns Also critical to step dummy dies along wafer circumferenceSlide 17 Loke, Wee & PfiesterAgilent TechnologiesWell Implants Lots of Transistor Variants core vs.

9 I/O FET s, core low-/nom-/high-VTvariants, native vs. implantedCoren-wellCoren-wellCorep-wellI /On-wellCoren-wellCorep-wellI/On-wellI/O p-wellCorenativeI/OnativeCoren-wellCorep -wellfree lunch!!!Slide 18 Loke, Wee & PfiesterAgilent TechnologiesWell Engineering Retrogradedwell dopant profile(implants before poly deposition)p-wellDepthSubstrateDopingDee per subsurface implant Extra dopants to prevent subsurface punchthrough under halos Prevent parasitic channel formation on active sidewall beneath source/drain Faster diffusers OK (B, As/P)Shallow & steep surface channel implant VTcontrol Slow diffusers critical (Ga, Sb)Very deep high-dose implant Latchup prevention Noise immunity Faster diffusers OK (B, As/P)STIoxideSTIoxideImplant order matters to prevent ion channeling, especially for the shallow implantSlide 19 Loke, Wee & PfiesterAgilent TechnologiesGate Oxidation Need two gate oxide tox s thin for core FET s & thick for I/O FET s Grow 1stoxide, strip oxide for core FET s, grow 2ndoxide Gate oxide is really made of silicon oxynitride (SiOxNy) N content prevents boron penetration from p+ poly to channel in pFET s Side benefit increased eoxSource.

10 Maex, IMEC (2002)Subroutine on Equipment Technology Gate oxide no longer furnace grown Multi-chamber cluster tools now ubiquitous Pre-oxidation clean, gate oxidation & poly/ARL deposition performed in separate chambers without breaking vacuum Better thickness & film compositional control (native SiO2grows instantly when exposed to air) Fast minutes-seconds per wafer vs. hours per wafer batchTopViewSlide 20 Loke, Wee & PfiesterAgilent TechnologiesPoly Gate DefinitionSi substrate Process control is everything resist & poly etch chamber conditioning is critical (lesson to remember: don t clean those residues in tea cups or woks) Way to get smaller CD s to trim more (requires tighter control) Dummification also necessary for poly maskpoly-Si123anti-reflection layer (ARL)gateoxideresistresistPattern resistTrim resist (oxygen ash)Etch gate stackpolygate Gate CD way smaller than lithography capability, even with mask tricksSlide 21 Loke, Wee & PfiesterAgilent TechnologiesSource/Drain & Channel Engineering Resulting structure has.