Introduction to IBIS (I/O Buffer Info Specification) …

1 Application Note 1111 An Introduction to ibis (I/O Buffer Information Specification) ModelingLiterature Number: SNLA046An Introduction to ibis (I/O Buffer InformationSpecification) ModelingINTRODUCTIONWith time to market becoming shorter and shorter, systemdesigners are struggling to release a product from concept toreality in a tightly budgeted time. The need to simulate be-fore prototyping is very essential and the ability to simulateand simulate accurately has heightened even more. But inorder to simulate a system level board, all components onthe board need to be modeled. Unfortunately many devicemodels are not readily available from (I/O Buffer Information Specification) is a BehavioralModeling Specification that is gaining world wide popularityas a standard format to generate device models. ibis solvesmany of the problems that prevented system designers fromobtaining semiconductor vendor s SPICE application note discusses various aspects of ibis in-cluding its history, advantages, compatibility, model genera-tion flow, data requirements in modeling the input/outputstructures and future Buffer Information Specification is a fast and accuratebehavioral method of modeling input/output buffers based onV/I curve data derived from measurement or full circuit simu-lation.

2 It uses a standardized software parsable format in theform of an ASCII file to store the Behavioral Informationneeded to model device characteristics of integrated can be used by almost any Simulators/EDA tools in theindustry. A wide range of Industry leaders support the ibis open forum. Below is a partial list of vendors supporting theIBIS method of model Incorporated (AMPredictor)Applied Simulation Technology (Apsim)Avanti (Meta I/O)Cadence Design System (DFSigNoise)HPEESof (LineSimPRO)INCASES (INSIDE, EXLIN)IntuSoft (IS_SPICE)Mentor Graphics (IS)Quantic EMC Inc (Greenfield)Veribest Systems (XTK/TLC)Zuken-RedacHISTORY OF IBISThe originator of ibis was Intel. Presently the standard is be-ing driven by the ibis forum with over 35 members consist-ing of EDA vendors, Computer manufacturers, Semiconduc-tor vendors and was released in April 1993.

3 Is capable ofmodeling standard TTL or CMOS type of I/O structure. InJune 1993 at the DAC (Design Automation Conference)show in Dallas, was released. The major changeswere the addition of more comments to the original was ratified in June 1994 at the DAC conference inSan Diego. is a considerable improvement Some of the added features are, Multiple rail sup-port (ex. V+ and V supply for RS-232), ECL, Terminatormodels, Open drain, Open collector, Differential I/O, Con-trolled slew rate and Definitions of complex package param-eters to name a added more comments to clarify and has beenratified December 1994. Today ibis is an approved standardwithin EIA (Electronic Industry Alliance) and is also knownunder has been ratified at DAC97. The committee is in theprocess of finalizing the development of the has various advanced features. Some of the addedfeatures are Driver selection, Diode stored charge, PackageModel extension, Electrical board description, Multi-stageDrivers, Series elements and more.

4 Improves uponclarification issues with EIG (Electronic Information Group) within EIA has beenactively working towards making ibis part of the IEC (Euro-pean standard). ibis has been accepted as IEC-62014-1(Sep 97) at the Tokyo International Standards software parser (known as the Golden Parser ) vali-dates the ibis model file. TheGolden Parserchecks thesyntax of the ibis model file to confirm that the data formatmeets the ibis specification. The object code of the parser isavailable for free from the forum. Simulator vendors mayalso purchase the source code for a is backwards compatible. So all models created todayusing the present version of the specification are guaranteedto work with future versions of ibis . The ibis forum is con-tinually defining new and improved ways of modeling com-plex and unique I/O OF IBISThe ibis model file protects proprietary information aboutthe modeled circuit as no process or circuit design informa-tion is disclosed.

5 A SPICE model on the other hand can dis-close substantial information that Semiconductor vendorsconsider to be confidential such as circuit nodal connectionsand process parameters. ibis models are accurate, asnon-linear aspects of I/O structures as well as package para-sitic and ESD structures are considered in the model param-eters. Since ibis is behavioral, the simulation time for anIBIS model can run 25x faster than a structural model(SPICE). ibis does not have non-convergence issues likeSPICE and can practically run on any Industry wide plat-forms as most EDA vendors support the ibis of the most popular uses of ibis is for Signal IntegrityAnalysis on system boards. The models are very easy tocreate as they can be made from bench measurements orfrom simulation is a registered trademark of National Semiconductor SemiconductorApplication Note1111 Syed B. HuqJune 1998An Introduction to ibis (I/O Buffer Information Specification) ModelingAN-1111 1998 National Semiconductor is a behavioral block diagram of ibis (Figure 1)and the pieces needed to create an Input and an STRUCTURE MODELI nformation needed to model the Input Structure is shown inFigure 2.

6 C__pkg, R__pkg and L__pkg are the package pa-rameters. Power__Clamp and GND__Clamp defines theESD structures on the Inputs. The V/I curve data definesthese clamp structures. C__comp is the input capacitance ofthe input STRUCTURE MODELI nformation needed to model the output structure is shown inFigure 3. Pullup defines VOH/IOH, Pulldown definesthe VOL/IOLand Ramp defines the dV/dT of the Rising andFalling 1. Behavioral Diagram of IBISAN012626-2 FIGURE 2. Input/Enable Structure ModelAN012626-3 FIGURE 3. Output Structure Pullup and Pulldown data are created from the V/Icurves. The remaining parameters are similar to the Inputstructure except that they define the package parasitic of theoutput pin as well as the output capacitance of the Pullup and Power__Clamp data are VCCrelative ,meaning that the voltage values are referenced to VCCandnot ground. So the voltages in the tables are derived fromthe equation: Vtable=VCC data is nec-essary for the simulator as the Pullup structure depends onthe voltage between the output and VCCand not the voltagebetween the output and ground Interconnect engineer can create a slow and a fast modelusing ibis .

7 The slow model is useful to determine flight timeand the fast model is useful to analyze overshoot, under-shoot, crosstalk, etc. By combining min IOH/IOLwith maxramp time and max package parameters, a slow model isgenerated. To create a fast model, the max IOH/IOL, minramp and minimum package information is GENERATION FLOWThe following steps are used in generating an ibis model. Allnecessary V/I and other parameters need to be either mea-sured on the bench, obtained from simulation or provided bythe semiconductor vendor. (Step 1)Measurements of package parameters can be made throughTDR (Time Domain Reflectometry) techniques if they are notavailable from the semiconductor vendor. V/I data can becollected using a curve tracer or programmable supply withsinking and sourcing capabilities. Clamp curves can be gen-erated by putting the device in TRI-STATE and sweepingthe I/O. For non TRI-STATE devices, the V/I curves are thesummation of the Clamp and required data is: R__pkg, L__pkg, C__pkg andC__comp for all Inputs and Outputs and and GND__Clamp (ESD structures ifpresent) for I/O.

8 Pullup, Pulldown and Ramp rates for Interconnect engineer then creates the ibis ASCII filefollowing the format defined in the ibis standard (Step 2).This can be done on a UNIX or DOS text ASCII model file is then checked by the Golden Parser for possible syntax errors (Step 3). If passed, the model isthen imported into a simulator and validated for accuracy(Step 4). Now the model is ready for 4shows thisflow in a graphical VALIDATION ON SIMULATORM odel validation is the final and critical step to ibis model-ing. Visual inspection, s2iplt checks, parser test, simulationof model under known loads, comparison of simulation datato bench/SPICE, edge rate and signal swing level verifica-tion are also done during this phase. National s InterfaceProducts Group validates the ibis models on two differentIBIS complaint models are primarily used for SI (Signal Integrity) Analy-sis. These are typically crosstalk, ringing, overshoot, under-shoot, mismatched impedance, reflections, line terminationanalysis, topology scheme analysis, design rule generationand multi-board is best suited for SI analysis on system boards requiringvery little run time (25X faster than SPICE).

9 AN012626-4 FIGURE 4. ibis Model Generation TRENDS OF IBISS ince its formation in 1993, ibis has improved it s specifica-tion by many folds. More complex modeling features andpossibly timing analysis may be added to future ibis speci-fications. DIE (Die Information Exchange) forum whichspecifies DIE information for MCM applications referencesIBIS as the Signal Integrity Analysis specification. FMF (FreeModel Forum), OMF (Open Model Forum), CFI (CADF ramework Initiative) are some of the other forums that ref-erences ibis for behavioral III (I/O Interface model for Ics) is another organizationworking on generating an I/O spec based on ibis but withadded SPICE syntax 93/67/NP( ibis and EMC simulation) is a task force as-signed to investigate the use of ibis models for EMC is also working with the JC-16B committee to defineSSTL and HSTL technology modeling using AND IBISN ational s various product lines are generating ibis modelstoday.

10 Interface Applications actively participates in ibis fo-rum meetings and was very instrumental in adding the Differ-ential I/O specification to modeling is accurate, easy to create and compatible ona wide rage of Simulation platforms. It solves the NO MODELS AVAILABLE problem in the industry. ibis hascreated a common Industry format for modeling using Be-havioral information and does not disclose any propietaryprocess parameters or circuit design SUPPORT POLICYNATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION. As used herein:1. Life support devices or systems are devices or sys-tems which, (a) are intended for surgical implant intothe body, or (b) support or sustain life, and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling, canbe reasonably expected to result in a significant injuryto the A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or SemiconductorCorporationAmericasTel: 1-800-272-9959 Fax: 1-800-737-7018 Email: SemiconductorEuropeFax: +49 (0) 1 80-530 85 86 Email: Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Fran ais Tel: +49 (0) 1 80-532 93 58 ItalianoTel: +49 (0) 1 80-534 16 80 National SemiconductorAsia Pacific CustomerResponse GroupTel: 65-2544466 Fax: 65-2504466 Email.