Introduction to IBIS (I/O Buffer Info Specification) …

1 Application Note 1111 An Introduction to ibis (I/O Buffer Information Specification) ModelingLiterature Number: SNLA046An Introduction to ibis (I/O Buffer InformationSpecification) ModelingINTRODUCTIONWith time to market becoming shorter and shorter, systemdesigners are struggling to release a product from concept toreality in a tightly budgeted time. The need to simulate be-fore prototyping is very essential and the ability to simulateand simulate accurately has heightened even more. But inorder to simulate a system level board, all components onthe board need to be modeled. Unfortunately many devicemodels are not readily available from (I/O Buffer Information Specification) is a BehavioralModeling Specification that is gaining world wide popularityas a standard format to generate device models.

2 ibis solvesmany of the problems that prevented system designers fromobtaining semiconductor vendor s SPICE application note discusses various aspects of ibis in-cluding its history, advantages, compatibility, model genera-tion flow, data requirements in modeling the input/outputstructures and future Buffer Information Specification is a fast and accuratebehavioral method of modeling input/output buffers based onV/I curve data derived from measurement or full circuit simu-lation. It uses a standardized software parsable format in theform of an ASCII file to store the Behavioral Informationneeded to model device characteristics of integrated can be used by almost any Simulators/EDA tools in theindustry.

3 A wide range of Industry leaders support the ibis open forum. Below is a partial list of vendors supporting theIBIS method of model Incorporated (AMPredictor)Applied Simulation Technology (Apsim)Avanti (Meta I/O)Cadence Design System (DFSigNoise)HPEESof (LineSimPRO)INCASES (INSIDE, EXLIN)IntuSoft (IS_SPICE)Mentor Graphics (IS)Quantic EMC Inc (Greenfield)Veribest Systems (XTK/TLC)Zuken-RedacHISTORY OF IBISThe originator of ibis was Intel. Presently the standard is be-ing driven by the ibis forum with over 35 members consist-ing of EDA vendors, Computer manufacturers, Semiconduc-tor vendors and was released in April 1993.

4 Is capable ofmodeling standard TTL or CMOS type of I/O structure. InJune 1993 at the DAC (Design Automation Conference)show in Dallas, was released. The major changeswere the addition of more comments to the original was ratified in June 1994 at the DAC conference inSan Diego. is a considerable improvement Some of the added features are, Multiple rail sup-port (ex. V+ and V supply for RS-232), ECL, Terminatormodels, Open drain, Open collector, Differential I/O, Con-trolled slew rate and Definitions of complex package param-eters to name a added more comments to clarify and has beenratified December 1994. Today ibis is an approved standardwithin EIA (Electronic Industry Alliance) and is also knownunder has been ratified at DAC97.

5 The committee is in theprocess of finalizing the development of the has various advanced features. Some of the addedfeatures are Driver selection, Diode stored charge, PackageModel extension, Electrical board description, Multi-stageDrivers, Series elements and more. improves uponclarification issues with EIG (Electronic Information Group) within EIA has beenactively working towards making ibis part of the IEC (Euro-pean standard). ibis has been accepted as IEC-62014-1(Sep 97) at the Tokyo International Standards software parser (known as the Golden Parser ) vali-dates the ibis model file. TheGolden Parserchecks thesyntax of the ibis model file to confirm that the data formatmeets the ibis specification.

6 The object code of the parser isavailable for free from the forum. Simulator vendors mayalso purchase the source code for a is backwards compatible. So all models created todayusing the present version of the specification are guaranteedto work with future versions of ibis . The ibis forum is con-tinually defining new and improved ways of modeling com-plex and unique I/O OF IBISThe ibis model file protects proprietary information aboutthe modeled circuit as no process or circuit design informa-tion is disclosed. A SPICE model on the other hand can dis-close substantial information that Semiconductor vendorsconsider to be confidential such as circuit nodal connectionsand process parameters.

7 ibis models are accurate, asnon-linear aspects of I/O structures as well as package para-sitic and ESD structures are considered in the model param-eters. Since ibis is behavioral, the simulation time for anIBIS model can run 25x faster than a structural model(SPICE). ibis does not have non-convergence issues likeSPICE and can practically run on any Industry wide plat-forms as most EDA vendors support the ibis of the most popular uses of ibis is for Signal IntegrityAnalysis on system boards. The models are very easy tocreate as they can be made from bench measurements orfrom simulation is a registered trademark of National Semiconductor SemiconductorApplication Note1111 Syed B.

8 HuqJune 1998An Introduction to ibis (I/O Buffer Information Specification) ModelingAN-1111 1998 National Semiconductor is a behavioral block diagram of ibis (Figure 1)and the pieces needed to create an Input and an STRUCTURE MODELI nformation needed to model the Input Structure is shown inFigure 2. C__pkg, R__pkg and L__pkg are the package pa-rameters. Power__Clamp and GND__Clamp defines theESD structures on the Inputs. The V/I curve data definesthese clamp structures. C__comp is the input capacitance ofthe input STRUCTURE MODELI nformation needed to model the output structure is shown inFigure 3. Pullup defines VOH/IOH, Pulldown definesthe VOL/IOLand Ramp defines the dV/dT of the Rising andFalling 1.

9 Behavioral Diagram of IBISAN012626-2 FIGURE 2. Input/Enable Structure ModelAN012626-3 FIGURE 3. Output Structure Pullup and Pulldown data are created from the V/Icurves. The remaining parameters are similar to the Inputstructure except that they define the package parasitic of theoutput pin as well as the output capacitance of the Pullup and Power__Clamp data are VCCrelative ,meaning that the voltage values are referenced to VCCandnot ground. So the voltages in the tables are derived fromthe equation: Vtable=VCC data is nec-essary for the simulator as the Pullup structure depends onthe voltage between the output and VCCand not the voltagebetween the output and ground Interconnect engineer can create a slow and a fast modelusing ibis .

10 The slow model is useful to determine flight timeand the fast model is useful to analyze overshoot, under-shoot, crosstalk, etc. By combining min IOH/IOLwith maxramp time and max package parameters, a slow model isgenerated. To create a fast model, the max IOH/IOL, minramp and minimum package information is GENERATION FLOWThe following steps are used in generating an ibis model. Allnecessary V/I and other parameters need to be either mea-sured on the bench, obtained from simulation or provided bythe semiconductor vendor. (Step 1)Measurements of package parameters can be made throughTDR (Time Domain Reflectometry) techniques if they are notavailable from the semiconductor vendor.