裸片到裸片接口IP的新疆域：芯片成功的需知

1 IP . Leong Zhang 2020 10 28 .. Synopsys Confidential Information 2020 Synopsys, Inc. 2.. 2027 1770 . ). 200,000. 180,000. 160,000. 140,000. 2027 . 1776 2018 705 . 120,000.. 100,000. 2030 260 . 80,000. 60,000. 7nm 3nm . IP . 40,000. 20,000. 0. 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027. IBS 2019 . Synopsys Confidential Information 2020 Synopsys, Inc. 3. Synopsys .. SerDes 112G 112G 112G.. 400/800G D2D D2D D2D .. D2D. DDR5. DDR5. DDR5 DDR5.. DDR5 . USR 56G XSR 112G HBI.. CPU. TCAM MP.. PCIe . Hardware root of trust . 100 TRNG . HBM. HBM. HBM . HBM. CXL DRAM PCIe/CXL DRAM. I/O. CXL AI HBM. CXL . HBM2e 3600 HBM3 6400. CCIX CXL . Synopsys Confidential Information 2020 Synopsys, Inc. 4. SiP SoC . Fragmented Market . interposer HBI.

2 / / MCM 112G USR. Synopsys DesignWare Die-to-Die IP .. Synopsys Confidential Information 2020 Synopsys, Inc. 5. Die . BER . SoC SoC. reticle size .. SKU . Radix Switch .. D2D. D2D. CPU CPU. D2D D2D. PCIe PCIe D2D. D2D. CPU CPU. D2D D2D. D2D. D2D. CPU CPU. DDR DDR. Synopsys Confidential Information 2020 Synopsys, Inc. 6. Die .. IO . I/O . SKU / Time-To-Market . Time-To-Market I/O SKU. FPGA ADAS RF + CPU FPGA . BB . DDR/HBM. D2D D2D. D2D. D2D. RF. D2D. D2D PHY. D2D PHY. PIPE PIPE r TRX.. JESD. FPGA.. JESD.. D2D. D2D. Fabric ADC. D2D. D2D. DAC D2D. D2D D2D. DDR/HBM. Synopsys Confidential Information 2020 Synopsys, Inc. 7. Disaggregate + Scale . IO. Die IO Die scale Die - 2 CPU Die . - CPU Die .. IO. - . - BER. FEC. BER . Synopsys Confidential Information 2020 Synopsys, Inc.

3 8.. Synopsys Confidential Information 2020 Synopsys, Inc. 9.. Synopsys Confidential Information 2020 Synopsys, Inc. 10. PHY .. 5 4 .. OIF CEI 56G 112G USR/XSR HBI OpenHBI AIB+ BoW. 112 Gbps 2 4 Gbps 6 Gbps pJ/bit pJ/bit . BER PAM-4 FEC . Substrate interposer .. 75 25 . Synopsys Confidential Information 2020 Synopsys, Inc. 11. InFO . /IO / . Silicon interposer Data Rate: Line Space: > , 4000 Pin Count Integrated Fanout (InFO). HBI+/AIB+ PHY. Post Fab RDL (Fanout). Cost & Complexity Data Rate: 56 Gbps Line Space: >2mm, 2500 Pin Count 112G USR/XSR PHY. organic Substrate Data Rate: 112 Gbps Line Space: >10mm Data Rates Die/Package Size, Density & IO Count Synopsys Confidential Information 2020 Synopsys, Inc. 12. 56G/112G USR/XSR PHY. NRZ PAM-4.

4 Synopsys Confidential Information 2020 Synopsys, Inc. 13. OIF . NRZ 56 Gbps,PAM-4 112 Gbps 56G NRZ. 112G PAM-4. OIF CEI-56G OIF CEI-112G. TX . CEI-56G-USR CEI-112G-MCM USR 250mVppd 2dB @ 28 GHz NRZ. 3D Stack Chip 6dB @ 28 GHz CNRZ XSR 600mVppd 25mm, no FEC/EQ 25mm, no FEC/EQ 3D Stack Chip CEI-56G-XSR CEI-112G-XSR . Chip OE Chip OE. 8dB @ 28 GHz NRZ. 4dB @ 14 GHz PAM-4. 10dB @ 28 GHz PAM-4 USR . 50mm, no connector Chip to Nearby OE 50mm, Lite FEC & CTLE or Chip OE XSR TX FFE/RX CTLE. CEI-56G-VSR CEI-112G-VSR. 10dB @ 14 GHz PAM-4. Chip Module 12-16dB @ 28 GHz PAM-4. Chip Module 112G FEC Replay . 10cm, 1 connector Chip to Pluggable Module FEC to relax BER 10-6 Chip to Pluggable Module . CEI-56G-MR Chip Chip CEI-112G-MR Chip Chip DLL.

5 15-25dB @ 14 GHz PAM-4 20dB @ 28 GHz PAM-4. 50cm, 1 connector C-C & Mid-Plane FEC to relax BER 10-5 C-C & Mid-Plane CEI-112G-MCM . CEI-56G-LR Chip Chip CEI-112G-LR Chord . Chip Chip 35dB @ 14 GHz PAM-4 28-30dB @ 28 GHz PAM-4. 100cm, 2 connectors BP or Passive Cu FEC to relax BER 10-4 BP or Passive Cu Synopsys Confidential Information 2020 Synopsys, Inc. 14. USR/XSR VSR MR/LR . 4 5 . Ultra/Extra Short Reach Very Short Reach Medium or Long Reach NRZ PAM-4 NRZ PAM-4 PAM-4. - GAUI . 3pJ 6pJ. PAM-4 . + . RX TX . AFE + ADC + DSP . DLL + CDR CDR .. RX Lane DLL + RX Lane RX Lane CDR CDR. phase align T Coil & RX+ T Coil & RX+ T Coil & RX+. De-serializer Samplers RTERM. De-serializer Samplers CTLE. RTERM. De-serializer DSP ADC CTLE VGA. RTERM.

6 RX- RX- RX- Equalizer Equalizer adaptation adaptation Synopsys Confidential Information 2020 Synopsys, Inc. 15.. OIF CEI 56G USR/XSR 112G XSR . USR/XSR SerDes on organic Substate Die 1 S Die 2. 112G E 112G. 5 FinFET IP . DDR. DDR. 112G R 112G. 112G D 112G. NRZ/PAM-4 112 Gbps E. C4 Bumps S C4 Bumps SoC (PMA Macro). TX/RX . + .. SI-PI . Synopsys Confidential Information 2020 Synopsys, Inc. 16. PHY Marco 4 . x16L x16L East-West Escapes North-South Escapes TX RX Raw PCS. Raw PCS Raw PCS. RX. 180 Flip x16L. connection to SoC x16L. 90 Flip TX. Raw PCS. x16L. TX. Raw PCS. x16L. Raw PCS TX . TX Raw PCS . x16L connection to SoC. Raw PCS ESD PHY PHY I/O Bump Raw PCS. connection to SoC. RX. x16L. 4 . RX. x16L Raw PCS Raw PCS Raw PCS Raw PCS Raw PCS.

7 TX RX TX TX RX. x16L x16L x16L x16L x16L. Synopsys Confidential Information 2020 Synopsys, Inc. 17.. TSMC N7 Test Chip Die KGD . IP . Voltage BIST . Die Die TX x16 RX x16. / . Phase . 5 Dies on 4-2-4 Substrate Multiple Channel Lengths 6 TX RX.. 5mm 15mm 25mm 50mm . 5 .. Synopsys Confidential Information 2020 Synopsys, Inc. 18.. 112G USR . Synopsys Confidential Information 2020 Synopsys, Inc. 19. DesignWare USR/XSR PHY .. 56 Gbps NRZ 112 Gbps PAM4 . 4 5 . PHY .. 1. 3 4 5. 2. Synopsys Confidential Information 2020 Synopsys, Inc. 20. HBI/AIB+ PHY. Synopsys Confidential Information 2020 Synopsys, Inc. 21. interposer . HBI AIB+ OpenHBI. interposer Silicon Bridge . HBI on interposer . DWORD DWORD DWORD DWORD. Die 1 Die 2. DWORD DWORD DWORD DWORD.

8 DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. AWORDX2 AWORDX2 AWORDX2 AWORDX2. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. DWORD DWORD BP_M_TEST[1] BP_M_TEST[0]. DWORD DWORD. BP_M_TEST[0] BP_M_TEST[1]. BP_VREF. BP_VREF. MASTER MASTER DWORD DWORD. DWORD DWORD VDDQ VAA. VAA VDDQ. MIDSTACK. EWR. PUB. WRCK WSI WSOd WSOh CAPTUR. EWR R WR. WSOb WSOf SnapCap f WSOh WSOd WSI WRCK. CAPTUR SHIFTW UPDATE. SnapCap f WSOf MIDSTACK. WSOb WIR. WR. UPDATE. ]. R. SHIFTW. P n PUB VDD. n RESET_. n P. CATTRI. ]. ]. TEMP[1. ]. WIR. SELECT. WSOc WSOg WSOg WSOc VDD BP_ZN WSOa WSOe SELECT TEMP[1 CATTRI RESET_ WRST_ TEMP[0 TEMP[2. ] ] n WSOe WSOa TEMP[2 TEMP[0 WRST_. BP_ZN BP_ZN. BP_ZN. VDD. VSS. VDD. DWORD DWORD. VSS. DWORD DWORD. DWORD DWORD DWORD DWORD.

9 DWORD DWORD. 4 FinFET IP . DWORD DWORD. DWORD DWORD DWORD DWORD. AWORDX2 AWORDX2. H. AWORDX2 AWORDX2. 4G. DWORD DWORD DWORD DWORD. HBM. HBM. DWORD DWORD DWORD DWORD. Z. Z. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. 4G. B 4G. DWORD DWORD. DWORD DWORD.. DWORD DWORD. DWORD DWORD. DWORD DWORD DWORD DWORD. I. DWORD DWORD DWORD DWORD. AWORDX2 AWORDX2. AWORDX2 AWORDX2. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. DWORD DWORD BP_M_TEST[1] BP_M_TEST[0]. DWORD DWORD. BP_M_TEST[0] BP_M_TEST[1]. BP_VREF. BP_VREF. MASTER DWORD DWORD. DWORD DWORD MASTER VAA VDDQ. VDDQ VAA. MIDSTACK. EWR. PUB. WRCK WSI WSOd WSOh CAPTUR. R WR. WSOb WSOf SnapCap f EWR. WSOh WSOd WSI. CAPTUR. WRCK SHIFTW UPDATE. SnapCap f WSOf MIDSTACK. WSOb WIR. WR. UPDATE.

10 ]. R. SHIFTW. P n PUB VDD. BP_ZN. n RESET_. n P. CATTRI. ]. ]. TEMP[1. ]. WIR. SELECT. WSOa WSOc WSOe WSOg WSOg WSOc SELECT TEMP[1 CATTRI RESET_ VDD WRST_ TEMP[0 TEMP[2. WSOe WSOa ] ] n BP_ZN BP_ZN. TEMP[2 TEMP[0 WRST_. BP_ZN. VDD. VSS. DWORD DWORD. VDD. VSS. DWORD DWORD. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. DWORD DWORD. m-Bumps m-Bumps DWORD DWORD. AWORDX2 AWORDX2. KGD . AWORDX2 AWORDX2. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD. Z. Z. DWORD DWORD DWORD DWORD. DWORD DWORD DWORD DWORD.. HBI PHY Channel of 80 TX + 80 RX. - - . interposer . Synopsys Confidential Information 2020 Synopsys, Inc. 22. DesignWare HBI PHY . interposer 1000 KGD .. (FSM).. I/O . TX . RX DLL . BIST . / .. PASS.. FAIL. VDD . I/O VDDTX/VDDRX.