ISD Cortex™-M0 ChipCorder ISD9160 Technical Reference …

1 ISD9160 Technical Reference manual Publication Release Date: Mar 30, 2016 - 1 - Revision ISD Cortex -M0 ChipCorder ISD9160 Technical Reference manual The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for Reference purposes of ISD ChipCorder microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 2 - Revision Table of Contents- TABLE OF CONTENTS- .. 2 1 GENERAL DESCRIPTION .. 6 2 FEATURES .. 7 3 PART INFORMATION AND PIN CONFIGURATION .. 10 Pin Configuration .. 10 ISD9160 LQFP 48 pin .. 10 Pin Description.

2 10 4 BLOCK DIAGRAM .. 15 5 FUNCTIONAL 16 ARM Cortex -M0 core .. 16 System Manager .. 17 Overview .. 17 System Reset .. 17 System Power Distribution .. 18 System Memory 19 System Manager Control Registers .. 21 System Timer (SysTick) .. 39 Nested Vectored Interrupt Controller (NVIC) .. 43 System Control Registers .. 83 Clock Controller and Power Management Unit (PMU) .. 90 Clock Generator .. 90 System Clock & SysTick Clock .. 91 Peripheral Clocks .. 92 Power Management .. 92 Clock Control Register Map .. 93 Clock Control Register Description .. 95 General Purpose I/O .. 111 Overview and Features .. 111 GPIO I/O Modes .. 111 GPIO Control Register Map .. 113 GPIO Control Register Description .. 114 Brownout Detection and Temperature Alarm .. 124 Brownout and Temperature Alarm Register Map .. 124 I2C Serial Interface Controller (Master/Slave) .. 129 Introduction .. 129 I2C Protocol Registers.

3 134 Register Mapping .. 137 Register Description .. 138 Modes of Operation .. 145 Data Transfer Flow in Five Operating Modes .. 146 PWM Generator and Capture Timer .. 152 Introduction .. 152 Features .. 153 PWM Generator Architecture .. 154 PWM-Timer Operation .. 154 ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 3 - Revision PWM Double Buffering, Auto-reload and One-shot Operation .. 156 Modulate Duty Cycle .. 156 Dead-Zone Generator .. 157 Capture Timer Operation .. 158 PWM-Timer Interrupt Architecture .. 159 PWM-Timer Initialization Procedure .. 159 PWM-Timer Stop Procedure .. 159 Capture Start Procedure .. 160 Register Map .. 161 Register Description .. 162 Real Time Clock (RTC) .. 177 Overview .. 177 RTC Features .. 177 RTC Block Diagram .. 178 RTC Function Description .. 179 Register Map .. 181 Register Description .. 182 Serial Peripheral Interface (SPI) Controller.

4 195 Overview .. 195 Features .. 195 SPI Block Diagram .. 195 SPI Function Descriptions .. 196 SPI Timing Diagram .. 204 SPI Configuration Examples .. 207 SPI Serial Interface Control Register Map .. 209 SPI Control Register Description .. 210 Timer Controller .. 219 General Timer Controller .. 219 Features .. 219 Timer Controller Block 220 Timer Controller Register Map .. 221 Watchdog Timer .. 227 Watchdog Timer Control Registers Map .. 229 UART Interface Controller .. 232 Overview .. 232 Features of UART controller .. 234 Block Diagram .. 235 IrDA Mode .. 237 LIN (Local Interconnection Network) mode .. 239 UART Interface Control Register Map .. 240 UART Interface Control Register Description .. 241 I2S Audio PCM Controller .. 262 Overview .. 262 Features .. 262 I2S Block Diagram .. 263 I2S Operation .. 264 FIFO operation .. 265 I2S Control Register Map .. 266 I2S Control Register Description.

5 267 ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 4 - Revision Cyclic Redundancy Check (CRC) Controller .. 278 Overview and Features .. 278 Operation .. 278 Example .. 278 CRC Controller Register Map .. 279 CRC Control Register Description .. 280 PDMA Controller .. 283 Overview .. 283 Features .. 283 Block Diagram .. 283 Function Description .. 284 PDMA Controller Register Map .. 285 PDMA Control Register Description .. 287 6 FLASH MEMORY CONTROLLER (FMC) .. 305 Overview .. 305 Features .. 305 Flash Memory Controller Block Diagram .. 306 Flash Memory Organization .. 307 Boot Selection .. 308 Data Flash (DATAF) .. 308 User Configuration (CONFIG) .. 309 In-System Programming (ISP) .. 311 ISP Procedure .. 311 Flash Control Register Map .. 314 Flash Control Register Description .. 315 7 ANALOG SIGNAL PATH BLOCKS .. 322 Audio Analog-to-Digital Converter (ADC).. 322 Functional Description.

6 322 Features .. 322 Block Diagram .. 322 Operation .. 323 ADC Register 325 ADC Register Description .. 326 Audio Class D Speaker Driver (DPWM) .. 334 Functional Description .. 334 Features .. 334 Block Diagram .. 334 Operation .. 334 DPWM Register Map .. 336 DPWM Register Description .. 337 Analog Comparator .. 342 Functional Description .. 342 Features .. 342 Block Diagram .. 342 Operational Procedure .. 343 Setup Procedure .. 343 ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 5 - Revision Register Map .. 344 Register Description .. 345 Analog Functional Blocks .. 349 Overview .. 349 Features .. 349 Register Map .. 349 VMID Reference Voltage Generation .. 351 GPIO Current Source Generation .. 353 LDO Power Domain Control .. 355 Microphone Bias Generator .. 358 Analog Multiplexer .. 362 Programmable Gain Amplifier .. 365 Capacitive Touch Sensing Relaxation Oscillator/Counter.

7 370 Oscillator Frequency Measurement and Control .. 374 Automatic Level Control (ALC) .. 379 Overview and Features .. 379 ALC Control Register Map .. 384 ALC Control Register Description .. 385 Biquad Filter (BIQ) .. 391 Overview and Features .. 391 BIQ Control Register Map .. 392 8 APPLICATION DIAGRAM .. 396 9 ELECTRICAL CHARACTERISTICS .. 397 Absolute Maximum Ratings .. 397 DC Electrical Characteristics .. 398 AC Electrical Characteristics .. 402 External 32kHz XTAL Oscillator .. 402 Internal Oscillator .. 402 Internal 16 kHz Oscillator .. 402 Analog Characteristics .. 403 Specification of ADC and Speaker Driver .. 403 Specification of PGA and BOOST .. 404 Specification of ALC an MICBIAS .. 405 Specification of LDO & Power management .. 406 Specification of Brownout Detector .. 407 Specification of Power-On Reset (VCCD) .. 407 Specification of Temperature Sensor .. 408 Specification of Comparator.

8 408 Reset Characteristics .. 408 10 PACKAGE DIMENSIONS .. 411 48L LQFP ( footprint ) .. 411 11 ORDERING INFORMATION .. 412 12 REVISION HISTORY .. 414 IMPORTANT NOTICE .. 415 ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 6 - Revision 1 GENERAL DESCRIPTION The ISD9160 is a system-on-chip product optimized for low power, audio record and playback with an embedded ARM Cortex -M0 32-bit microcontroller core. The ISD9160 embeds a Cortex -M0 core running up to 50 MHz with 145K-byte of non-volatile flash memory and 12K-byte of embedded SRAM. It also comes equipped with a variety of peripheral devices, such as Timers, Watchdog Timer (WDT), Real-time Clock (RTC), Peripheral Direct Memory Access (PDMA), a variety of serial interfaces (UART, SPI/SSP, I2C, I2S), PWM modulators, GPIO, Analog Comparator, Low Voltage Detector and Brown-out detector. The ISD9160 comes equipped with a rich set of power saving modes including a Deep Power Down (DPD) mode drawing less than 1 A.

9 A micro-power 16 KHz oscillator can periodically wake up the device from deep power down to check for other events. A Standby Power Down (SPD) mode can maintain a real time clock function at less than 10 A. For audio functionality the ISD9160 includes a Sigma-Delta ADC with 92dB SNR performance coupled with a Programmable Gain Amplifier (PGA) capable of a maximum gain of 61dB to enable direct connection of a microphone. Audio output is provided by a Differential Class D amplifier (DPWM) that can deliver 1W of power to an 8 speaker. The ISD9160 provides eight analog enabled general purpose IO pins (GPIO). These pins can be configured to connect to an analog comparator, can be configured as analog current sources or can be routed to the SDADC for analog conversion. They can also be used as a relaxation oscillator to perform capacitive touch sensing. ISD9160 Technical Reference manual Release Date: Mar 30, 2016 - 7 - Revision 2 FEATURES Core ARM Cortex -M0 core runs up to 50 MHz.

10 One 24-bit System tick timer for operating system support. Supports a variety of low power sleep and power down modes. Single-cycle 32-bit hardware multiplier. NVIC (Nested Vector Interrupt Controller) for 32 interrupt inputs, each with 4-levels of priority. Serial Wire Debug (SWD) supports with 2 watchpoints/4 breakpoints. Power Management Wide operating voltage range from to Power management Unit (PMU) providing four levels of power control. Deep Power Down (DPD) mode with sub micro-amp leakage (<1 A). Wakeup from Deep Power Down via dedicated WAKEUP pin or timed operation from internal low power 16 KHz oscillator. Standby mode with limited RAM retention and RTC operation (<10 A). Wakeup from Standby can be from any GPIO interrupt, RTC or BOD. Sleep mode with minimal dynamic power consumption. 3V LDO for operation of external 3V devices such as serial flash. Flash EPROM Memory 145K bytes Flash EPROM for program code and data storage.