KeyStone Architecture Gigabit Ethernet (GbE) Switch …

1 KeyStone Architecture Gigabit Ethernet (GbE) Switch Subsystem User's Guide Literature Number: SPRUGV9D. November 2010 Revised June 2013. Contents 16. 1 Introduction .. 17. Purpose of the Peripheral .. 18. Features .. 18. Gigabit Ethernet Switch Subsystem Functional Block Diagram .. 19. Industry Standard(s) Compliance Statement .. 21. 2 Architecture .. 22. Clock 23. Gigabit Switch Subsystem Clock .. 23. SGMII SerDes Reference 23. MDIO Clock .. 23. IEEE 1588 Time Synchronization Clock .. 23. GMII Clock .. 23. Memory Map .. 24. Gigabit Ethernet Switch Architecture .. 24. Streaming Packet Interface .. 25. Transmit Streaming Packet Interface .. 25. Receive Streaming Packet Interface .. 26. Media Access Controller Submodule Architecture .. 27. Data Receive Operations.

2 27. Data Transmission .. 28. MAC Receive FIFO Architecture .. 32. Statistics Submodule Architecture .. 33. Accessing Statistics Registers .. 33. Statistics Interrupts .. 33. Receive Statistics Descriptions .. 34. Transmit (Only) Statistics Descriptions .. 39. Receive and Transmit (Shared) Statistics Descriptions .. 42. Time Synchronization Submodule Architecture .. 43. KeyStone II Time Synchronization Submodule Architecture .. 44. Time Synchronization Submodule Components .. 44. Time Synchronization Events .. 46. Time Synchronization Initialization .. 51. Detecting and Processing Time Synchronization Events .. 51. Address Lookup Engine (ALE) Submodule Architecture .. 52. ALE Table .. 53. Reading Entries from the ALE Table .. 53. Writing Entries to the ALE Table.

3 53. ALE Table Entry Types .. 54. ALE Packet Forwarding Process .. 58. ALE Learning 64. Serial Gigabit Media Independent Interface (SGMII) Architecture .. 65. SGMII Receive Interface .. 65. SGMII Transmit 65. Modes of Operation .. 65. 2 Contents SPRUGV9D November 2010 Revised June 2013. Submit Documentation Feedback Copyright 2010 2013, Texas Instruments Incorporated Digital Loopback .. 65. SGMII to PHY 66. SGMII to SGMII with Auto-Negotiation Configuration .. 66. SGMII to SGMII with Forced Link Configuration .. 67. Management Data Input/Output (MDIO) Architecture .. 68. Global PHY Detection and Link State Monitoring .. 68. PHY Register User Access .. 68. Writing Data to a PHY Register .. 69. Reading Data from a PHY Register .. 70. MDIO 70. MDIO User Access Interrupts.

4 70. Initializing the MDIO Module .. 70. KeyStone I Serializer/Deserializer (SerDes) Architecture .. 71. KeyStone II Serializer/Deserializer (SerDes) Architecture .. 71. Reset Considerations .. 71. Initialization .. 71. GbE Switch Subsystem Initialization Procedure .. 71. Interrupt Support .. 72. Interrupt 72. Power 72. 3 Registers .. 73. Summary of Modules .. 74. Gigabit Ethernet (GbE) Switch Subsystem Module .. 88. Ethernet Switch Subsystem Identification and Version Register (ES_SS_IDVER).. 89. Serial Gigabit Media Independent Interface (SGMII) module .. 90. SGMII Identification and Version Register (SGMII_IDVER) .. 91. SGMII Software Reset Register (SGMII_SOFT_RESET).. 92. SGMII Control Register (SGMII_CONTROL) .. 93. SGMII Status Register (SGMII_STATUS).

5 94. SGMII Advertised Ability Register (SGMII_MR_ADV_ABILITY) .. 95. SGMII MODE .. 95. SGMII Link Partner Advertised Ability Register (SGMII_MR_LP_ADV_ABILITY) .. 96. Management Data Input/Output (MDIO) 97. MDIO Version Register (MDIO_VERSION) .. 98. MDIO Control Register (MDIO_CONTROL) .. 99. PHY Alive Status Register (MDIO_ALIVE) .. 100. PHY Link Status Register (MDIO_LINK).. 101. MDIO Link Status Change Interrupt (Unmasked) Register (MDIO_LINKINTRAW) .. 102. MDIO Link Status Change Interrupt (Masked) Register (MDIO_LINKINTMASKED) .. 103. MDIO User Command Complete Interrupt (Unmasked) Register (MDIO_USERINTRAW) .. 104. MDIO User Command Complete Interrupt (Masked) Register (MDIO_USERINTMASKED) .. 105. MDIO User Command Complete Interrupt Mask Set Register (MDIO_USERINTMASKSET).

6 106. MDIO User Command Complete Interrupt Mask Clear Register (MDIO_USERINTMASKCLEAR) . 107. MDIO User Access Register 0 (MDIO_USERACCESS0) .. 108. MDIO User PHY Select Register 0 (MDIO_USERPHYSEL0) .. 109. MDIO User Access Register 1 (MDIO_USERACCESS1) .. 110. MDIO User PHY Select Register 1 (MDIO_USERPHYSEL1) .. 111. Ethernet Switch Module .. 112. Gigabit Ethernet (GbE) Switch 113. GbE Switch Identification and Version Register (CPSW_IDVER) .. 116. GbE Switch Control Register (CPSW_CONTROL) .. 117. Emulation Control Register (EM_CONTROL) .. 118. Statistics Port Enable (STAT_PORT_EN) .. 119. SPRUGV9D November 2010 Revised June 2013 Contents 3. Submit Documentation Feedback Copyright 2010 2013, Texas Instruments Incorporated Priority Type Register (PTYPE).

7 121. KeyStone I and KeyStone II MAC Short Gap Threshold Register (GAP_THRESH) .. 122. Transmit FIFO Start Words Register (TX_START_WDS) .. 123. Flow Control Register (FLOW_CONTROL) .. 124. Port 0 Source Identification Register (P0_CPPI_SRC_ID) .. 125. Port 0 VLAN Register (P0_PORT_VLAN).. 126. Port 0 Receive Packet Priority to Header Priority Mapping Register (P0_RX_PRI_MAP) .. 127. Port 0 Receive Maximum Length Register (P0_RX_MAXLEN) .. 128. Port 1 Max Blocks Register (P1_MAX_BLKS).. 129. Port 1 Block Count Register (P1_BLK_CNT) .. 130. Port 1 VLAN Register (P1_PORT_VLAN).. 131. Port 1 Transmit Header Priority to Switch Priority Mapping Register (P1_TX_PRI_MAP) .. 132. MAC1 Source Address Low Register (MAC1_SA_LO).. 133. MAC1 Source Address High Register (MAC1_SA_HI).

8 134. Port 1 Time Sync Control Register (P1_TS_CTL) .. 135. Port 1 Time Sync Sequence ID and LTYPE Register (P1_TS_SEQ_LTYPE) .. 137. Port 1 Time Sync Control Register 2 (P1 _TS_CTL2) .. 138. Port 1 Time Sync Control Register and LTYPE2 (P1 _TS_CTL_LTYPE2) .. 139. Port 1 Time Sync VLAN LTYPE Register (P1_TS_VLAN_LTYPE) .. 140. Port 2 Max Blocks Register (P2_MAX_BLKS).. 141. Port 2 Block Count Register (P2_BLK_CNT) .. 142. Port 2 VLAN Register (P2_PORT_VLAN).. 143. Port 2 Transmit Header Priority to Switch Priority Mapping Register (P2_TX_PRI_MAP) .. 144. MAC2 Source Address Low Register (MAC2_SA_LO).. 145. MAC2 Source Address High Reserved Register (MAC2_SA_HI) .. 146. Port 2 Time Sync Control Register (P2_TS_CTL) .. 147. Port 2 Time Sync Sequence ID and LTYPE Register (P2_TS_SEQ_LTYPE).

9 149. Port 2 Time Sync VLAN LTYPE Register (P2_TS_VLAN_LTYPE) .. 150. Port 2 Time Sync Control Register 2 (P2 _TS_CTL2) .. 151. Port 2 Time Sync Control Register and LTYPE2 (P2 _TS_CTL_LTYPE2) .. 152. KeyStone II Port 3 & 4 Register Descriptions .. 153. Port 3 Max Blocks Register (P3_MAX_BLKS).. 153. Port 3 Block Count Register (P3_BLK_CNT) .. 154. Port 3 VLAN Register (P3_PORT_VLAN).. 155. Port 3 Transmit Header Priority to Switch Priority Mapping Register (P3_TX_PRI_MAP) .. 156. MAC3 Source Address Low Register (MAC3_SA_LO).. 157. MAC3 Source Address High Register (MAC3_SA_HI) .. 158. Port 3 Time Sync Control Register (P3 _TS_CTL) .. 159. Port 3 Time Sync Sequence ID and LTYPE Register (P3_TS_SEQ_LTYPE) .. 160. Port 3 Time Sync VLAN LTYPE Register (P3_TS_VLAN_LTYPE).

10 161. Port 3 Time Sync Control and LTYPE2 Register (P3 _TS_CTL_LTYPE2) .. 162. Port 3 Time Sync Control Register 2 (P3 _TS_CTL2) .. 163. Port 4 Max Blocks Register (P4_MAX_BLKS).. 164. Port 4 Block Count Register (P4_BLK_CNT) .. 165. Port 4 VLAN Register (P4_PORT_VLAN).. 166. Port 4 Transmit Header Priority to Switch Priority Mapping Register (P4_TX_PRI_MAP) .. 167. MAC4 Source Address Low Register (MAC4_SA_LO).. 168. MAC4 Source Address High Register (MAC4_SA_HI) .. 169. Port 4 Time Sync Control Register (P4 _TS_CTL) .. 170. Port 4 Time Sync Sequence ID and LTYPE Register (P4_TS_SEQ_LTYPE) .. 171. Port 4 Time Sync VLAN LTYPE Register (P4_TS_VLAN_LTYPE) .. 172. Port 4 Time Sync Control Register and LTYPE2 (P4 _TS_CTL_LTYPE2) .. 173. Port 4 Time Sync Control Register 2 (P4 _TS_CTL2).