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Lab 1: Schematic and Layout of a NAND gate
3. Close the “About what’s New Window”. 4. If you get a licensing issue, select “always” 5. If you ever reopen the layout view from the library manager, you will most likely open it in Layout L (the window title will be Virtuoso Layout Suite L and you will be missing the bottom toolbar). To open Layout XL, select . Launch -> Layout XL
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Lab 1: Schematic and Layout of a NAND gate
www.doe.carleton.caGet familiar with the Cadence Virtuoso environment. Draw a schematic of a simple NAND gate and simulate it. Draw layout of a NAND gate using cell library, then run a design rule check (DRC), extract, run a layout versus schematic (LVS) and simulate the extracted circuit. Compare the schematic and extracted simulations.
Lab 1: Schematic and Layout of a NAND gate
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