Transcription of LVDS Application and Data Handbook - TI.com
1 lvds Application and DataHandbookHigh-Performance Linear ProductsTechnical StaffPrinted on Recycled PaperLiterature Number: SLLD009 November 2002 IMPORTANT NOTICET exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI s termsand conditions of sale supplied at the time of order warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI s standard warranty.
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4 TI is not responsible or liable forsuch altered of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments IncorporatedContentsiiiNovember 2002 SLLD009 ContentsChapter 1 data Transmission Basics1 1.. Transmission Lines and Characteristics1 2.
5 Single-Ended vs Differential1 4.. Point-to-Point, Multidrop, and Multipoint Buses1 6.. Benefits of Standardization1 7.. 644 vs 644a vs LVDM vs M-LVDS1 8.. lvds /M- lvds Summary1 9.. Chapter 2 lvds and M- lvds Line Circuit Characteristics and Features2 1.. Driver Output Voltage2 1.. Differential Input Voltage Threshold2 2.. Common-Mode Voltage Range2 3.. Signaling Rate2 5.. Power Consumption2 7.. Supply Voltage2 9.. Reliability2 9.. Integrated Terminations2 10.. Fault Tolerance and Failsafe Receivers2 11.. Live Insertion (Hot Plugging)2 11.. Chapter 3 Application Examples3 1.. Receiving Single-Ended Logic Levels3 1.
6 Receiving Other Differential Signals3 4.. Adjusting lvds Output Levels3 7.. Chapter 4 Product Selection4 1.. Cross-Point Switches4 1.. Serializers/Deserializers4 2.. Line Driver and Receivers4 3.. Line Transceivers4 4.. Line Receivers4 4.. Line Drivers4 6.. Repeaters4 7.. Cross Reference4 7.. Chapter 5 Product Specifications5 1.. General Information5 1.. data Sheets5 3.. Chapter 6 Design Guidelines and Tools6 1.. Common Problems6 1.. Printed-Circuit Board Guidelines6 2.. Powering lvds Devices6 5.. Termination Techniques6 6.. Unused Pins6 8.. Connectors and Cables6 8.. Design Tools6 9.
7 Other Design Help6 15.. List of IllustrationsivNovember 2002 SLLD009 Conclusion6 16.. References6 16.. Chapter 7 Testing Guidelines7 1.. Introduction7 1.. Using the Eye Pattern7 1.. Jitter Measurements7 2.. Eye Mask7 3.. Bit-Error-Rate Test (BERT)7 4.. Electromagnetic Compatibility Testing7 5.. Troubleshooting7 6.. Common lvds Problems7 7.. Signal Integrity7 7.. Random Jitter7 8.. Deterministic Jitter7 8.. Time Domain Reflectometry (TDR)7 10.. Conclusion7 11.. References7 11.. Glossary7 12.. List of IllustrationsFigureTitlePage1 1 Approximate Signaling Rate vs Transmission Distance for Various Interfaces1 1.
8 1 2 Initial-Wave Circuit Model1 3.. 1 3 The Line-Load Boundary1 3.. 1 4 Reflected-Wave Example1 4.. 1 5 Single-Ending Interface Circuit Schematic Diagram1 5.. 1 6 Differential Interface Circuit Schematic Diagram1 5.. 1 7 A Point-to-Point data Interchange Circuit1 6.. 1 8 A Multidrop data Interchange Circuit1 7.. 1 9 A Multipoint data Interchange Circuit1 7.. 1 10 TIA/EIA-644 Driver Output Test Circuit1 8.. 1 11 TIA/EIA-644-A Driver Output Test Circuit1 8.. 1 12 Load Power Comparison of Differential Signals1 10.. 1 13 TIA/EIA Standard Voltage Ranges1 11.. 2 1 VOD Definition2 1.
9 2 2 Circuit Used to Measure the Driver Common-Mode Output Voltage2 1.. 2 3 lvds and M- lvds Differential Input Voltage Thresholds2 2.. 2 4 Common-Mode Rejection Test of a Differential Line Receiver2 4.. 2 5 TIA/EIA-644-A Signal Quality Recommendations2 6.. 2 6 MC100 LVEP111 and SN65 LVDS116 Power Comparison2 8.. 2 7 Differential Driver Circuit Model2 8.. 2 8 Normalized Power vs Speed Comparison of Voltage-Mode and Current-Mode Driver2 9.. 2 9 Power-Up/Down Waveforms2 12.. 3 1 Circuit Blocks for Receiving Single-Ended Logic Signals3 1.. List of IllustrationsvNovember 2002 SLLD0093 2 Simple Input Attenuator3 2.
10 3 3 Single-Ended Logic Levels3 3.. 3 4 Voltage Divider Reference Circuit3 4.. 3 5 100-Mbps IEEE-1394 Transceiver With LVDS3 5.. 3 6 ECL-to-CMOS Conversion With the SN65 LVDS3483 6.. 3 7 CML-to-CMOS Translation With the SN65 LVDS3483 6.. 3 8 RS-422/485-to-CMOS Translator With the SN65 LVS3483 6.. 3 9 SN65 LVDS31 Output Current vs Voltage3 7.. 3 10 Equivalent Circuit of SN65 LVDS31 Steady-State Differential Output3 7.. 3 11 Eye Patterns for Multiple Drivers and 100- Loads3 8.. 3 12 Eye Patterns With Four Parallel Drivers Into a 27- Load3 9.. 3 13 Precompensation Circuits With Two Drivers3 9.
