LVDS Owner’s Manual - Texas Instruments

1 lvds owner s ManualIncluding High-Speed CML and signal ConditioningHigh-Speed Interface TechnologiesOverview 9-13 Network Topology 15-17 SerDes Architectures 19-29 Termination and Translation 31-38 Design and Layout Guidelines 39-45 Jitter Overview 47-58 Interconnect Media and signal conditioning 59-75I/O Models 77-82 Solutions for Design Challenges owner s ManualIncluding High-Speed CML and signal ConditioningFourth Edition20084 Introduction ..7 High-Speed Interface Technologies Differential Signaling Technology .. lvds Low-Voltage Differential Signaling .. CML Current-Mode Logic .. Low-Voltage Positive-Emitter-Coupled Logic .. Selecting An Optimal Technology ..12 Network Topology .. Point-to-Point .. Multipoint / Multidrop .. SerDes Architectures .. Mixing Signaling Technologies .. Selecting an Interface Technology ..17 SerDes Architectures .. Introduction .. Parallel Clock SerDes.

2 Embedded Clock (Start-Stop) Bits SerDes .. 8b/10b SerDes .. FPGA-Attach SerDes .. Applications ..23 Parallel Clock SerDes ..23 Embedded Clock (Start-Stop) Bits SerDes ..24 8b/10b SerDes ..26 FPGA-Attach SerDes .. Comparison Overview .. Summary ..29 Termination and Translation .. Terminations and Impedance Matching .. Multidrop and Multipoint .. AC Coupling .. DC Balance ..33 Selecting a Capacitor .. Translation .. Failsafes ..37 M- lvds Failsafes ..38 Design and Layout Guidelines .. PCB Transmission Lines .. Transmission Loss .. PCB Vias .. Backplane Subsystem .. Decoupling ..44 Jitter Overview .. Introduction ..47 Random Jitter Characteristics ..47 Deterministic Jitter ..48 Duty Cycle Distortion ..49 Inter-Symbol Interference ..50 Periodic Jitter .. Additional Jitter Sources ..52 Effect of Input Capacitance ..53 FEXT/NEXT ..53 Systems Susceptible to Crosstalk.

3 54 Bit Error Rate .. Pattern Dependencies and Eye Diagrams ..55 Eye Masks ..57 Bathtub Curves and Eye Contours ..57 Interconnect Media and signal conditioning .. Physical and Electrical Cable Characteristics .. signal - conditioning Characteristics ..63 Media Losses in Cables and PCB Traces ..63 Pre-Emphasis and De-Emphasis Drivers ..64 Equalization ..65 Two Types of Equalizer Circuits ..66 Passive: Power-Saver Equalizers ..66 Active Equalizers ..66 Fixed Equalizers ..67 Variable Equalizers Allow Control ..67 Adaptive Equalizers ..67 Crosstalk ..68 Reflections .. Using Pre- and De-Emphasis and Equalizers Together . Random Noise .. Re-clocking Receivers (Re-clockers) .. Bit Error Rate (BER) and Jitter (Random and Deterministic) ..72 Lossy Media Compensated by Equalization ..72 Pre-Emphasis Eye Diagrams ..74 PE/EQ Combination ..75 Semiconductor I/O Models .. Input/Output Buffer Information Specification.

4 Behavioral Diagram of IBIS .. 3-State Output Model .. Creating IBIS Models .. Scattering Parameters (S Parameters) .. SPICE Models ..82 Solutions for Design Challenges .. Clock Distribution and signal conditioning ..83 Point-to-Point Clock Distribution ..83 Multipoint Clock Distribution ..83 Clock Conditioners .. System Clock Distribution ..86 ATCA-Synchronization Clock Interface ..86 MicroTCA-Synchronization Clock Interface .. Complementing FPGA Performance ..88 Extending SerDes Enables FPGAs ..88 Load Capacitance is Critical ..89 lvds Translation .. Broadcast Video .. Extending the Reach of SerDes ..92 Identifying Cable-Extender-Chipset Benefits ..93 Typical Transmission Distance Gains ..94 Extending signal Transmission with conditioning . 94 Power-Saver Equalizers .. M- lvds : A High-Speed, Short-Reach Alternative to Redundancy .. Testability of High-Speed Differential Networks.

5 98 Functional Testing ..98 Loopback .. DVI / HDMI ..101 High Data Rates and Longer Cost-Effective Cables 101 Compensation for Skin Effects and Dielectric Losses ..101 Appendix of Technical References .. Websites and lvds Applications .. Analog Edge and signal Path Designer Articles .. Outside Publications .. Application Note References ..104 Index .. Acronyms .. Glossary of Common Datasheet Parameters .. Semiconductor s lvds owner s Manual , first published in spring 1997, has been the industry s go-to design guide over the last decade. The owner s Manual helped lvds grow from the original IEEE Standard for Low-Voltage Differential Signaling ( lvds ) for Scalable Coherent Interface (SCI) into the workhorse technology it is is now pervasive in communications networks and used extensively in applications such as laptop computers, office imaging, industrial vision, test and measurement, medical, and automotive.

6 It provides an attractive solution - a small-swing differential signal for fast data transfers at significantly reduced power and with excellent noise immunity. Along with the applications, lvds continued to evolve over the last decade to meet specific requirements such as Bus lvds and Multipoint lvds . For example, the latest lvds products are capable of data rates in excess of 3 Gbps while still maintaining the low power and noise immunity , many applications require even faster data rates and longer transmission paths. Therefore, designers should consider technologies such as Current-Mode Logic (CML) and signal conditioning for both lvds and CML. That is why this new Fourth Edition includes practical design techniques for these technologies as well as LVPECL and owner s Manual provides useful and current information. It begins with a brief overview of the three most common high-speed interface technologies ( lvds (with variants B- lvds and M- lvds ), CML, and LVPECL) a review of their respective characteristics, and a section on selecting the optimal technology for an application.

7 The Manual then covers relevant topics such as level translation, jitter, signal conditioning , and suggested design approaches. This practical informa-tion will help you select the right solution for today s interface design Interface Technologies Overview Differential Signaling TechnologyThere are plenty of choices when selecting a high-speed differential signaling technology. Differential technologies generally share certain characteristics but vary widely in performance, power consumption, and target applications. Table 1-1 lists various attributes of the most common differential signaling 1-1. Industry Standards for Various lvds TechnologiesIndustry standards bodies define lvds and M- lvds technologies in specifications ANSI/TIA/EIA-644A and ANSI/TIA/EIA-899, respectively. Some vendor datasheets claim lvds I/Os (or pseudo- lvds ) but in fact may not meet the required common mode or some other important parameter.

8 Therefore, compliance to the lvds specification TIA/EIA-644A is an important Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) are widely used terms through-out the industry, although neither technology conforms to any standard controlled by an official standards organization. Implementations and device specifications will therefore often vary between vendors. AC coupling is used extensively which helps resolve threshold differences that might otherwise cause compatibility that all of the technologies listed are differential and thus share the advantages common to differential signaling such as excellent noise immunity and low device-generated switching StandardMaximum Data RateOutput Swing (VOD)Power Gbps 350 mVLowLVPECLN/A10+ Gbps 800 mVMedium to HighCMLN/A10+ Gbps 800 mVMediumM-LVDSTIA/EIA-899250 Mbps 550 mVLowB-LVDSN/A800 Mbps 550 mVLowDriverCurrent SourceReceiver= mACross Section of Differential Pair= 350 mV100 Figure 1-1.

9 lvds Driver and Receiver10 A typical lvds driver receiver pair is shown in Figure 1-1. A (nominal) mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100 termination resulting in a (nominal) 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to This combination provides excellent noise margins and tolerance to common-mode shifts between the driver and receiver. Changing the current direction results in the same amplitude but opposite polarity at the receiver. Logic ones and zeros are generated in this manner. CML and LVPECL have a similar architecture but with different strength current sources and termination schemes. Figure 1-2. Differential SignalingFrom this simple diagram in Figure 1-2, the advantages common to all differential signaling technologies can be seen.

10 First, note that the current source is always on and routed in different directions to drive logic ones and zeros. This always-on characteristic eliminates the switching-noise spikes and EMI resulting from turning high-current transistors on and off (as required in single-ended technologies). Secondly, the two lines of the differential pair are adjacent to each other providing a considerable amount of noise immunity. Noise from crosstalk or EMI that is absorbed in one of the pair will also appear in the adjacent line. Since the receiver responds to the difference between the two channels, common-mode noise that appears on both lines of the pair will cancel at the receiver. Also, as the two adjacent lines carry equal current, but in opposite directions, EMI generation is lvds Low-Voltage Differential SignalingThe 350 mV typical signal swing of lvds consumes only a small amount of power and therefore lvds is a very efficient technology, delivering performance at data rates up to Gbps.