MOSFET/IGBT DRIVERS THEORY AND APPLICATIONS

1 IXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr. 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-5036271 MOSFET/IGBT DRIVERSTHEORY AND APPLICATIONSBy Abhijit D. Pathak 2001 IXYS CorporationIXAN00101. MOSFET and igbt MOSFET Models and critical Turn-on and Turn-off phenomenon and their Power losses in Drivers2. Types of IC Gate Techniques available to boost current Techniques available to generate negative bias during Need for under-voltage Overload and Short Circuit Protection3. Isolation Employing Charge-pump and Bootstrap Examples of use of Opto-couplers in practical Driver Examples using transformers in practical Driver Circuits4. IXYS Line of MOSFET/IGBT Technical details of all IXYS Features and Advantages of IXYS Applying IXYS DRIVERS in various topologies5.

2 Practical Considerations6. ConclusionIXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr. 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-50362721. INTRODUCTIONM odern Power Electronics makes generous use of MOS-FETs and IGBTs in most APPLICATIONS and, if the presenttrend is any indication, the future will see more and moreapplications making use of MOSFETs and sufficient literature is available on characteris-tics of MOSFETs and IGBTs, practical aspects of drivingthem in specific circuit configurations at different powerlevels and at different frequencies require that design en-gineers pay attention to a number of attempt is made here to review this subject with someillustrative examples with a view to assist both experienceddesign engineers and those who are just initiated into thisdiscipline.

3 MOSFET AND igbt TECHNOLOGYDue to the absence of minority carrier transport, MOS-FETs can be switched at much higher frequencies. Thelimit on this is imposed by two factors: transit time of elec-trons across the drift region and the time required to chargeand discharge the input Gate and Miller derives its advantages from MOSFET and BJT. Itoperates as a MOSFET with an injecting region on itsDrain side to provide for conductivity modulation of theDrain drift region so that on-state losses are reduced,especially when compared to an equally rated high volt-age far as driving igbt is concerned, it resembles a MOS-FET and hence all turn-on and turn-off phenomena com-ments, diagrams and Driver circuits designed for drivingMOSFET apply equally well to an igbt .

4 Therefore, whatfollows deals only with MOSFET +CoCpCCGDN+GATE ElectrodeSOURCEMETALIZATIONP-BASERBDBCN- DRIFTD epletion boundariesFig. (1A) MOSFET cell internal structureFig. (1B) Cross sectional view of N-Channel MOSFET showing various inter-junction capacitancesCCCGSDSGDN+PN-N+N+PSOURCEGAT EPARASITIC BJTDRAINDRAIN BODY DEPLETION LAYERINTERNAL BODY DIODEOVGSA ctualLinearizedgm =IDDRAIN CURRENTGS(th)VGSVIDIDVGSFig. (2) Transfer characteristics of a power MOSFET MODELS AND CRITICAL PARAMETERSFig. (1A) shows the internal cell structure of a DMOSMOSFET. As can be seen, the Gate to Source Capaci-tance consists of three components, namely, Cp, the com-ponent created by the Gate Electrode over the P-baseregion; CN+, due to the overlap of the Gate Electrode abovethe N+ source region and, CO, arising due to the proximityof the Gate Electrode to the source metallization.

5 In fact,all these are added to yield CGS, which we call Gate-to-Source Capacitance. It is this total value of capacitancethat needs to be first charged to a critical threshold volt-age level VGS(th), before Drain Current can begin to Gate-to-Drain capacitance, CGD, is the overlap ca-pacitance between the Gate electrode and the N-drift Drainregion. CGD is sometimes referred to as the Miller ca-pacitance and contributes most to the switching speedlimitation of the MOSFET. The junction capacitance be-tween the drain to the P-Base region is CDS. The P-Baseregion of the MOSFET is shorted to the N+ source. Fig.(2) shows curve of ID (Drain Current) versus VGS (Gate SourceIXAN0010 IXYS Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr.)

6 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-5036273 Voltage). The graph has a slope (ID/ VGS) equal to gm,which is called transconductance. Please note that theactual relationship between VGS and ID is shown by dottedline and it can be observed that in the vicinity of VGS(th), therelationship between VGS and ID is parabolic in nature: ID= K [VGS-VGS(th)]2 , for Power MOSFETs, it is appropriate to con-sider the relationship to be linear for values of VGS aboveVGS(th). The manufacturer s data sheet value of VGS(th) is speci-fied at 25 oC. Fig. (3A) shows a symbol of N-Channel MOSFET and anequivalent model of the same with three inter-junction para-sitic capacitances, namely: CGS, CGD and CDS.

7 I have shownall these as variable as they indeed are. For example theCGD, decreases rapidly as the Drain to Source voltage rises,as shown in Fig. (3B). In Fig. (3B), the high value of CGD iscalled CGDh, while the low value of CGD is termed CGDl. Fig.(1B) shows another cross-sectional view of a MOSFET with all these capacitances. In addition, It also shows theinternal body diode and the parasitic Turn-on and Turn-off Turn-on PhenomenonTo understand Turn-on and Turn-off phenomena of the PowerMOSFET, we will assume clamped inductive switching asit is the most widely used mode of operation. This is shownin Fig. (4A) and Fig. (4B). A model of MOSFET is shownwith all relevant components, which play a role in turn-onand turn-off events. As stated above, MOSFET s Gate toSource Capacitance CGS needs to be charged to a criticalvoltage level to initiate conduction from Drain to Source.

8 Afew words of explanation will help understand Fig. (4A)and Fig. (4B). The clamped inductive load is being shownby a current source with a diode D connected antiparallelacross the inductor. The MOSFET has its intrinsic internalGate resistance, called RGint. As described above, the in-ter-junction parametric capacitances (CGS, CGD and CDS)are shown and connected at their proper points. VDD repre-sents the DC Bus voltage to the Drain of the MOSFET through the clamped inductive load. The Driver is suppliedby Vcc of value Vp and its ground is connected to thecommon ground of VDD and is returned to the Source ofthe MOSFET. The output from the Driver is connected tothe Gate of the MOSFET through a resistor when a positive going pulse appears at the input ter-minal of the Driver, an amplified pulse appears at the out-put terminal of the Driver with an amplitude Vp.

9 This is fedto the Gate of the MOSFET through RGext. As one can seethe rate of rise of voltage, VGS, over Gate and Source termi-nals of the MOSFET is governed by value of the total resis-tance in series (Rdr+RGext+RGint) and total effective value ofcapacitance (CGS+CGD). Rdr stands for the output sourceimpedance of the Driver. Rgext is the resistance one gener-ally puts in series with the Gate of a MOSFET to controlthe turn-on and turn-off speed of the (3A) Symbol and equivalent circuit of a MOSFETS ymbol ofN-Channel MOSFETDGSGCGDGSCGRDSCDSRDS(on)intVDSGSVF ig. (3B ) C variation Vwith respect toDSDSV =GDCGDCCGDhlGDFig (4A) A MOSFET being turned on by a driver in a clamped inductive + Corporation; 3540 Bassett Street; Santa Clara, CA 95054; Tel: 408-982-0700; Fax: 408-496-0670 IXYS Semiconductor GmbH; Edisonstr.

10 15; D-68623; Lampertheim, Germany; Tel: +49-6206-503-0; Fax: +49-6206-5036274 The waveforms drawn in Fig. (5) show variation of differentparameters with respect to time, so as to clearly explainthe entire turn-on sequence. In Fig. (4A) and Fig. (4B), theFree Wheeling Diode D is assumed to be ideal with zeroreverse recovery current. The waveforms shown in Fig. 5are based on this time zero to t1, (CGS+CGDl) is exponentially chargedwith a time constant T1=(Rdr+RGext+RGint)x(CGS+CGDl), untilGate-to-source voltage reaches VGS(th). In this time period,neither the Drain voltage nor the Drain current are affected, Drain voltage remains at VDD and Drain current has notcommenced yet. This is also termed turn-on delay. Notethat between 0 to t1, as VGS rises, IGS falls exponentially,more or less like a mirror image of VGS, because from thepoint of view of circuit analysis, it is an RC time t1, as the Gate-to-Source voltage rises aboveVGS(th), MOSFET enters linear region as shown in Fig.