MULTISTAGE AMPLIFIER - MIT

1 Spring 2007 Lecture 241 Lecture 24 MULTISTAGE Amplifiers (I) MULTISTAGE multi-stage voltage MULTISTAGE voltage current AMPLIFIER stagesReading Assignment:Howe and Sodini, Chapter 9, Sections Spring 2007 Lecture 2421. Introduction What amplifying stages should be used and in what order? What devices should be used, BJT or MOSFET? How is biasing to be done?Issues:Most often, single stage AMPLIFIER does not accomplish design goals: Need more gain than could be provided by a single stage Need to adapt to specified RSand RLto maximize efficiency MULTISTAGE Spring 2007 Lecture 243 Summary of single stage AMPLIFIER characteristicsCurrent bufferCommon BaseVoltage bufferCommon CollectorTranscon-ductance amplifierCommon EmitterCurrent bufferCommon GateVoltage BufferCommon DrainTranscon-ductance amplifierCommon SourceKey FunctionRoutRinAvo, AioStage)//(ocomvorrgA =ro//rocAvo gmgm+gmb 1gm+gmbAio 1 Avo= gm(ro//roc)mbmgg+1roc//[ro(1+gmRS)] rro//rocAvo 1 Aio 1()LocooRrrr//// +1gm+RS omg1roc//[ro(1+gmr //RS())]Differences between BJT s and MOSFETsr = ogm gmb gmgm=ICVth> gm=2WL CoxIDro=VAIC> ro=1 Spring 2007 Lecture 2442.

2 CMOS MULTISTAGE voltage AmplifierGoals: High voltage gain, Avo High input resistance, Rin Low output resistance, RoutGood starting point: Common-Source stage: Rin= Avo=-gm(ro//roc), probably insufficient Rout= (ro//roc), too Spring 2007 Lecture 245 Add second CS stage to get more gain:CMOS MULTISTAGE voltage AMPLIFIER (contd.) Rin= Avo=gm1(ro1//roc1) gm2(ro2//roc2) Rout= (ro2//roc2), still too highAdd CD stage at output (to reduce Rout): Rin= Avo=gm1ro1||roc1()gm2ro2||roc2()gm3gm3+g mb3 Rout=1gm3+ Spring 2007 Lecture 2463. BiCMOS MULTISTAGE voltage AMPLIFIER Rin2 Rout1+Rin2 Rin2 Rout1 r 2ro1||roc1<<1 How about adding a CE stage following the CS stage?Avo(CE) > Avo(CS) because ro(BJT) > ro(MOSFET), ||roc1>>Rin2=r 2CS stage is best first stage, since Rin= .However, inter-stage loading degrades gain:There is a voltage divider between stagesAdditional gain provided by the CE stage is mostly lost to inter-stage + vout+ (ro1 roc1) Av1vin1Av2vin2(ro2 roc2)+ + + + Spring 2007 Lecture 247 BiCMOS MULTISTAGE voltage AMPLIFIER (contd.)

3 Use two CS stages, but add CC stage at output:Since, in general gm(BJT) > gm(MOSFET), Routcould be better than CD output stage if ro2||roc2is not too large. Otherwise, CD output stage is ||roc2,Rin3=r 3+ o3ro3||roc3||RL()Inter-stage loading:Then, inter-stage loss:Rin3 Rout2+Rin3=r 3+ o3ro3||roc3||RL()ro2||roc2+r 3+ o3ro3||roc3||RL()Better than trying to use a CE stage, but still pretty good thing is that Routhas improved:Rout=Rout3=1gm3+Rout2 o3=1gm3+ro2||roc2 o3vsRLRSCS CSCC vinr3 + o3(ro3 roc3 RL)+ vout+ vin3(ro2 roc2) Av1Av2vinro2 roc2+ + + gm3 o3 +1+ Spring 2007 Lecture 248 BiCMOS MULTISTAGE voltage AMPLIFIER (contd.)What is the best order?Since Rin(CD)= , best to place CD first:Better voltage buffer: cascade CC and CD output stagesInter-stage loading:Rin3 Rin3+Rout2=1 Rin4 Rin4+Rout3=r 4+ o4ro4||roc4||RL()1gm3+gmb3+r 4+ o4ro4||roc4||RL() 1 The output resistance is excellent:Rout=Rout4=1gm4+Rout3 o4=1gm4+1 o4gm3+gmb3()Av1Av2vin(ro2 roc2)vinvin3vin3vin4vin4voutvsCS CSCD CCr4 + o4(RL ro roc)(gm3 + gmb3) o4(gm3 + gmb3)1 RLRS1gm41++ + + ++ + + + Spring 2007 Lecture 2494.

4 BiCMOS current bufferGoals: Unity current gain, Ai=1 Very low input resistance, Rin Very high output resistance, RoutStart with a common-base stage: Aio= 1 Rin=1gm Rout=roc||ro1+gmr ||RS()[]{}Note that if RSis high enough , Rout roc||( oro).Can we increase Routfurther by adding a second CB stage? Spring 2007 Lecture 2410 BiCMOS current buffer(contd).CB-CB Current BufferNowRout=Rout2=roc2||ro21+gm2r 2||Rout1()[]{}Plugging in Rout1 roc1|| ( o1roc1).Rout=roc2||ro21+gm2r 2||roc1|| o1ro1()[]{}But, since r 2<< roc1|| ( 1roc1), thenRout=roc2||ro21+gm2r 2()[] roc2|| o2ro2()Did not improve anything!The base current limits the number of CB stages that can improve the output resistance to just the CG stage has no gate current, cascade it with the CB stageisRLRS iout iin1 iin2iin2iin1[gm2ro2(r2 o1ro1 roc1)] roc2 CBCB o1ro1 Spring 2007 Lecture 2411 BiCMOS current buffer(contd).CB-CG Current BufferRout=Rout2=roc2||ro21+gm2 Rout1()[]Plugging in Rout1 roc1|| ( o1roc1).

5 Rout=roc2||ro2gm2roc1|| o1ro1()[]Now Routhas improved by about gm2ro2, but only to the extent that roc2is high iin1 iin2iin2iin1[gm2ro2( o1ro1 roc1)] roc2 CBCG o1ro1 Spring 2007 Lecture 24125. Coupling AMPLIFIER Stages Advantages Can select bias point for optimum operation Can select bias point close to the mid-point of the power rails for maximum voltage swing Disadvantages To approximate AC short, large capacitors are needed and they consume large COUPLINGC apacitors that have large enough value behave as AC short, so the signal goes through but bias is independent for each , CD-CC voltage VAssumes VBE = VVGS = Spring 2007 Lecture 2413 Coupling AMPLIFIER Stages (contd.)DIRECT COUPLING: share bias points across , CD-CC voltage buffer: Advantages No capacitors needed compact Disadvantages Bias point shared:constrains designs. Bias shifts from stage to stage and can stray too far from center of range Generally requires level shifting to bring signal back to center of VAssumes VBE = VVGS = Spring 2007 Lecture 2414 Coupling AMPLIFIER Stages (contd.)

6 SOLUTION: use PMOS CD stage for level VAssumes VBE = VVGS = Spring 2007 Lecture 2415 Coupling AMPLIFIER Stages (contd.)Summary of DC shifts through AMPLIFIER stages:AmplifierTypeTransistor TypeCommonSource/CommonEmitter(CS/CE)Com monGate/CommonBase(CG/CB)CommonDrain/Com monCollector(CD/CC)NMOS npnpnpiSUPV+V OUTINPMOSiSUPV+V+V OUTOUTOUTINININV iSUPiSUPV V+INiSUPV V+INiSUPV V+V+OUTOUTINV iSUPV+OUTOUTINV iSUPiSUPV+V OUTINiSUPV+V OUTINiSUPV+V OUTINiSUPV+V Spring 2007 Lecture 2416 What did we learn today?Summary of Key Concepts To achieve design goals, MULTISTAGE amplifiers are often needed In MULTISTAGE amplifiers, different stages are used to accomplish different goals voltage gain: common-source, common emitter voltage buffer: common drain, common collector Current buffer: common gate, common base In MULTISTAGE amplifiers, attention must be paid to inter-stage loading to avoid unnecessary losses Must select compromise bias, Must pay attention to bias shift from stage to stag